Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

• US 6,473,818 B1
• Filed: 09/09/1998
• Issued: 10/29/2002
• Est. Priority Date: 09/09/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lai, Po-shen, Chiang, John, Niu, Autumn J., Kuo, Jerry Chun-Jen
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): Backer, Firmin
• Application Number:
  US09/150,038
• Time in Patent Office: 1,511 Days
• Field of Search: 710/129, 710/128, 710/131, 710/61, 711/156, 711/149, 711/150, 711/168, 395/856, 395/858, 395/859, 365/230.05
• US Class Current: 711/168
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

Claims

1. A method in a network interface device, the method comprising:

receiving data frames based on a first clock domain at a first interface of the network interface device;

writing the data frames into a random access memory in the network interface based on the first clock domain;

changing a single bit of a write pointer value in response to each occurrence of the writing step;

reading stored data from the random access memory based on a second clock domain independent from the first clock domain;

changing a single bit of a read pointer value in response to each occurrence of the reading step;

forwarding the read data based on the second clock domain to a second interface on the network interface device;

comparing the read pointer value and the write pointer value; and

selectively setting one of a full and empty flag based on the comparing step;

writing the data to the random access memory based on the binary write address value.

2. The method of claim 1, wherein the read and write pointer values are gray coded pointer values.

3. The method of claim 1, wherein the comparing step comprises determining the difference between the read pointer value and the write pointer value.

4. The method of claim 1, wherein the writing step comprises:

decoding the write pointer value to a binary write address value; and

writing the data to the random access memory based on the binary write address value.

5. The method of claim 4, wherein the reading step comprises:

decoding the read pointer value to a binary read address value; and

reading the data from the random access memory based on the binary read address value.

6. The method of claim 1, wherein the step of changing a single bit of the write pointer value comprises changing the single bit to obtain a predetermined write pointer value corresponding to a wrap-around condition in the random access memory.

7. The method of claim 1, wherein the step of changing a single bit of the read pointer value comprises changing the single bit to obtain a predetermined read pointer value corresponding to a wrap-around condition in the random access memory.

8. The method of claim 1, wherein the comparing step includes comparing the read pointer value and the write pointer value independent of the first and second clock domains.

9. A network interface device, comprising:

a first interface configured to bi-directionally transmit data, wherein the first interface operates according to a first clock domain;

a second interface configured to bi-directionally transmit data, wherein the second interface operates according to a second clock domain;

a random access memory;

a write controller configured for writing data received from the first interface to the random access memory according to the first clock domain, the write controller including a write counter configured for changing a single bit of a write pointer value in response to writing the data into a corresponding memory location in the random access memory;

a read controller configured for reading stored data from the random access memory and outputting the read data to the second interface according to the second clock domain independent from the first clock domain, the read controller including a read counter configured for changing a single bit of a read pointer value in response to reading the stored data from a corresponding memory location in the random access memory; and

a comparison circuit for selectively determining one of a full condition and an empty condition in the random access memory based on the write pointer value and the read pointer value, independent of the first and second clock domains.

10. The network interface device of claim 9, wherein the write counter and the read counter are gray code counters.

11. The network interface device of claim 10, wherein the comparison circuit determines the full condition and the empty condition based on a determined difference between the read pointer value and the write pointer value and a predetermined random access memory size.

12. The network interface device of claim 10, further comprising:

a write decoder configured for decoding the write pointer value into a binary memory address value; and

a read decoder configured for decoding the read pointer value into a binary memory address value.

13. The network interface device of claim 9, wherein the read counter and the write counter are modulo counters relative to a size of the random access memory.

14. A network interface for passing data frames comprising:

a host bus interface, wherein the host bus interface operates according to a host clock domain;

a network media interface, wherein the network media interface operates according to a network clock domain;

a first random access memory partition;

a second random access memory partition;

a first write controller configured for writing data received from the host bus interface to the first random access memory partition according to the host clock domain, the first write controller including a first write counter configured for changing a single bit of a first write pointer value in response t o writ in g the data in to a corresponding memory location in the first random access memory partition;

a first read controller configured for reading stored data from the first random access memory partition and outputting the read data to the network media interface according to the network clock domain independent from the host clock domain, the first read controller including a first read counter configured for changing a single bit of a first read pointer value in response to reading the stored data from a corresponding memory location in the first random access memory partition;

a comparison circuit configured for selectively determining one of a full condition and an empty condition in the first random access memory partition based on the first write pointer value and the first read pointer value, independent of the host and network clock domains;

a second write controller configured for writing data received from the net work media interface to the second random access memory partition according to the network clock domain, the second write controller including a second write counter configured for changing a single bit of a second write pointer value in response to writing the data into a corresponding memory location in the second random access memory partition;

a second read controller configured for reading stored data from the second random access memory partition and outputting the read data to the host bus interface according to the host clock domain independent from the network clock domain, the second read controller including a second read counter configured for changing a single bit of a second read pointer value in response to reading the stored data from a corresponding memory location in the second random access memory partition; and

the comparison circuit further configured for selectively determining one of a full condition and an empty condition in the second random access memory partition based on the second write pointer value and the second read pointer value, independent of the host and network clock domains.

15. The network interface device of claim 14, further comprising a first decoder and a second decoder for converting the first read pointer value and the first write pointer value into binary values corresponding to memory locations in the first random access memory partition, respectively.

16. The network interface of claim 14, further comprising a media access control supplying the network clock domain and a bus interface unit supplying the host clock domain from a host bus.

17. The network interface device of claim 14, wherein the first and second write counters and the first and second read counters are gray code counters.

18. The network interface device of claim 17 wherein the first read counter and the first write counter are modulo counters relative to a size of the first random access memory partition.

19. The network interface device of claim 14, further comprising a first decoder and a second decoder for converting the second read pointer value and the second write pointer value into binary values corresponding to memory locations in the second random access memory partition, respectively.

20. The network interface device of claim 17 wherein the second read counter and the second write counter are modulo counters relative to a size of the second random access memory partition.