Apparatus and method for controlling secure communications between peripheral components on computer buses connected by a bridge circuit

• US 6,473,825 B1
• Filed: 01/12/2000
• Issued: 10/29/2002
• Est. Priority Date: 01/12/2000
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Lynch, Carolyn A., Blasdel, Michael J., Hale, Robert R., Worley, James F.
• Primary Examiner(s): Dharia, Rupal
• Application Number:
  US09/481,331
• Time in Patent Office: 1,021 Days
• Field of Search: 710/305-317, 710/200, 713/200, 713/201
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices

Abstract

An apparatus for and a method of controlling secure communication between peripheral components in a communication system. The security level of each peripheral component address in the communication system is fixed. When a message is communicated, a bus access arbiter (122) detects the address of the originating peripheral component, and an address detector (110, 114) detects the address of the destination peripheral component. An address comparison circuit (116) determines whether the address of the destination peripheral component is an address to which the originating peripheral component is permitted to communicate. The address comparison circuit (116) is responsive to the address of the destination peripheral component being an address to which the originating peripheral component is permitted to communicate by permitting communication of messages from the originating peripheral component. The address comparison circuit (116) is further responsive to the address of the destination peripheral component not being an address to the which the originating peripheral component is permitted to communicate by generating an error signal, preventing communication of further messages from the originating peripheral component.

Claims

1. A method of controlling communication between a first peripheral component located on a first computer bus and a second peripheral component located on a second computer bus, the first and second computer buses being connected by a bridge circuit, said method comprising the steps of:

(a) in response to placing onto the first computer bus of a message from the first peripheral component addressed to the second peripheral component, determining the addresses of the first and second peripheral components;

(b) determining the bus on which the second peripheral component is located;

(c) if the second peripheral component is located on the second computer bus, applying the message to the bridge circuit;

(d) determining whether the address of the second peripheral component is an address to which the first peripheral component is permitted to communicate;

(e) if the address of the second peripheral component is not an address to which the first peripheral component is permitted to communicate, preventing communication of further messages from the first peripheral component; and

(f) if the address of the second peripheral component is an address to which the first peripheral component is permitted to communicate, permitting the bridge circuit to pass messages from the first peripheral component.

2. A method as claimed in claim 1, wherein step (b) comprises determining whether the address of the second peripheral component is on a listing of addresses of peripheral components to which the first peripheral component is permitted to communicate.

3. A method as claimed in claim 1, wherein step (b) comprises determining whether the address of the second peripheral component is in a look-up table of addresses of peripheral components to which the first peripheral component is permitted to communicate.

4. A method as claimed in claim 1, wherein step (c) comprises shutting down the first peripheral component.

5. A method as claimed in claim 1, wherein step (c) comprises sending an error message to a maintenance processor to cause the maintenance processor to shut down the first peripheral component.

6. Apparatus for controlling communication between a first peripheral component located on a first computer bus and a second peripheral component located on a second computer bus, said apparatus comprising:

a bridge circuit connecting the first computer bus and the second computer bus;

a first address detector for detecting the address of the first peripheral component;

a second address detector for detecting the address of the second peripheral component and the bus on which the second peripheral component is located; and

an address comparison circuit for determining whether the address of the second peripheral component is an address to which the first peripheral component is permitted to communicate, said address comparison circuit being responsive to the address of the second peripheral component not being an address to which the first peripheral component is permitted to communicate by preventing passage of further messages from the first peripheral component through the bridge circuit, and being further responsive to the address of the second peripheral component being an address to which the first peripheral component is permitted to communicate by permitting passage of messages from the first peripheral component through the bridge circuit.

7. Apparatus as claimed in claim 6, wherein said address comparison circuit comprises a look-up table of addresses of peripheral components to which the first peripheral component is permitted to communicate, and a comparer for comparing the address of the second peripheral component with addresses in said look-up table.