Partition of on-chip memory buffer for cache

• US 6,473,835 B2
• Filed: 01/23/2002
• Issued: 10/29/2002
• Est. Priority Date: 08/31/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David Arnold
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Anderson, Matthew D.
• Application Number:
  US10/055,408
• Publication Number:
  US 20020062418A1
• Time in Patent Office: 279 Days
• Field of Search: 711/122, 711/128, 711/207, 711/117, 711/202, 711/205, 711/206
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed

Abstract

A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the cache is left unused, although the cache has the same memory array size as a typical n-way associative cache. The extra column of data in the cache is organized as an independent logical translation look-aside buffer (TLB) that is n-way associative. Thus, there is no separate TLB array for the cache, rather, the TLB is contained within the data cache array. In this way, the cache can be implemented with a single chip, and can be of relatively large size, on the order of 8 MB or more.

Claims

1. A computer system comprising:

at least one central processor unit;

a main memory;

a first cache at a first cache level for use by said at least one central processing unit, said first cache comprising a translation lookaside buffer (TLB) and a first cache memory array; and

a second cache at a second cache level for use by said at least one central processing unit, said second cache level being higher than said first cache level, said second cache comprising a second cache memory array and second cache control logic, said second cache memory array being an array of n columns and m rows, wherein a first portion of said second cache memory array having n−

p of said n columns is used for storing data and a second portion of said second cache memory array having p of said n columns is used for storing pairs of virtual address portions and real address portions for at least some data in the first portion of said second cache memory array, wherein (n−

2)≧

p≧

1, said first and second portions of the second cache memory array being disjoint;

wherein said second cache control logic receives at least a portion of a virtual address generated by said central processor unit and receives output of said translation lookaside buffer comprising at least a portion of a real address corresponding to said virtual address;

wherein if a virtual address generated by said central processor unit is contained in said translation lookaside buffer, said second level cache control logic selects an entry in said first portion of said second cache memory array using said at least a portion of a virtual address generated by said central processor unit and said output of said translation lookaside buffer;

wherein if a virtual address generated by said central processor unit is not contained in said translation lookaside buffer, said second level cache control logic selects an entry in said second portion of said second cache memory array using said at least a portion of a virtual address generated by said central processor unit to obtain an address pair comprising a virtual address portion and a real address portion, and subsequently selects an entry in said first portion of said second cache memory array using said at least a portion of a virtual address generated by said central processor unit and said real address portion obtained from said second portion of said second cache memory array.

2. The computer system of claim 1, wherein p=1.

3. The computer system of claim 1, wherein each row of said second portion of said second cache memory array contains p*q said address pairs, wherein q>

1.

4. The computer system of claim 3, further comprising:

p*q comparators, each comparator operating to compare a respective virtual address portion of an address pair from a selected row of said second portion of said second cache memory array with a corresponding portion of said virtual address generated by said central processor unit and producing a logic output; and

selection logic coupled to the logic outputs of said p*q comparators which operates to select a real address portion of an address pair having a virtual address portion identical to said corresponding portion of said virtual address generated by said central processor unit.

5. The computer system of claim 3, wherein p=1.

6. The computer system of claim 3, wherein said central processor unit and said first cache are embodied in a single integrated circuit chip.

7. A method of operating a computer system having at least one central processor unit, a main memory, a translation lookaside buffer, a first cache at a first level, d and a second cache at a second level higher than said first level, said second cache comprising a second cache memory array and second cache control logic, said second cache memory array being an array of n columns and m rows, wherein a first portion of said second cache memory array having n−

p of said n columns is used for storing data and a second portion of said second cache memory array having p of said n columns is used for storing address pairs, each address pair comprising a virtual address portion and a real address portion, for at least some data in the first portion of said second cache memory array, wherein (n−

2)≧

p≧

1, said first and second portions of the second cache memory array being disjoint, said method comprising the steps of;

generating a virtual address for a data reference with said CPU;

accessing said translation lookaside buffer to translate said virtual address to a real address;

if an entry corresponding to said virtual address is contained in said translation lookaside buffer, then translating said virtual address for a data reference to a real address for the data reference using said translation lookaside buffer, and accessing an entry in said first portion of said second cache, using said real address translated using said translation lookaside buffer; and

if an entry corresponding to said virtual address is not contained in said translation lookaside buffer, then accessing said second portion of said second cache to translate said virtual address for a data reference to a real address for the data reference, and subsequently using said real address translated using said second portion of said second cache to access an entry in said first portion of said second cache.

8. The method of operating a computer system of claim 7, further comprising the steps of:

if an entry corresponding to said virtual address is not contained in said second portion of said second cache, then accessing main memory to translate said virtual address to a real address.

9. The method of operating a computer system of claim 7, wherein p=1.

10. The method of operating a computer system of claim 7, wherein each row of said second portion of said second cache memory array contains p*q said address pairs, wherein q>

1.

11. The method of operating a computer system of claim 10, wherein p=1.

12. The method of operating a computer system of claim 7, wherein accessing said second portion of said second cache to translate said virtual address for a data reference to a real address for the data reference comprises:

decoding said virtual address to select a row of said second cache;

obtaining a plurality of address pairs from said selected row of said said second portion of said second cache;

comparing each respective portion of a virtual address from an address pair obtained from said selected row with a corresponding portion of said virtual address for a data reference; and

selecting a portion of a real address of an address pair having a portion of a virtual address identical to the corresponding portion of said virtual address for a data reference.