Method for controlling memory access on a machine with non-uniform memory access and machine for implementing such a method
First Claim
1. A method for controlling memory access on a machine with non-uniform memory access distributed over several modules, each module comprising one or more processors CPU for executing tasks on a virtual or physical addressing space by means of effective addresses generating logical page numbers to which it is possible to make physical page numbers correspond in the memory by means of a correlation table, the generation of a logical page number causing a task to have a first-level page-fault type exception when the logical page number is absent from the correlation table, comprisinga first step of activating, following each first-level page-fault type exception, a function (Trace), which records the value of an effective address that has generated the logical page number that has caused the exception, a date when the exception is caused, an identifier of the task using the effective address, an identifier of the processor executing the task, and a physical page number corresponding to the logical page number that has caused the exception;
- and wherein the activating of the function (Trace) is called from within the task having the exception and executed by the one or more processors.
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Accused Products
Abstract
On a machine with non-uniform memory access distributed over several modules, each module includes one or more processors for executing tasks on a virtual or physical addressing space by effective addresses generating logical page numbers to which it is possible to make physical page numbers correspond in the memory by a correlation tale. The generation of a logical page number causes a first-level page-fault type exception when the logical page number is absent from the correlation table. The method includes a step for activating a function (Trace), following each first-level page-fault type exception, a trace function, which records the value of the effective address that has generated the logical page number that has caused the exception, the date when the exception is caused, an identifier of the task using the effective address, an identifier of the processor executing the task and the physical page number corresponding to the logical page number that has caused the exception.
6 Citations
20 Claims
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1. A method for controlling memory access on a machine with non-uniform memory access distributed over several modules, each module comprising one or more processors CPU for executing tasks on a virtual or physical addressing space by means of effective addresses generating logical page numbers to which it is possible to make physical page numbers correspond in the memory by means of a correlation table, the generation of a logical page number causing a task to have a first-level page-fault type exception when the logical page number is absent from the correlation table, comprising
a first step of activating, following each first-level page-fault type exception, a function (Trace), which records the value of an effective address that has generated the logical page number that has caused the exception, a date when the exception is caused, an identifier of the task using the effective address, an identifier of the processor executing the task, and a physical page number corresponding to the logical page number that has caused the exception; - and
wherein the activating of the function (Trace) is called from within the task having the exception and executed by the one or more processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
locating the logical page number in said effective address;
searching the correlation table for the logical page number; and
performing the following steps if the logical page number is not found in said correlation table;
(a) deriving a physical page number in said effective address;
(b) searching a second correlation table for said physical page number;
(c) determining whether said second correlation table stores the logical page number in relation to said physical page number; and
(d) modifying the correlation table to store said physical page number in association with the logical page number based on an outcome of said determining step.
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16. An apparatus of r controlling memory access on a machine with non-uniform memory access distributed over several modules, each module comprising one or more processors CPU for executing tasks on a virtual or physical addressing space by means of effective address generating logical page numbers to which it is possible to make physical page numbers correspond in the memory by means of a correlation table, the generation of a logical page number causing a task to have a first-level page-fault type exception when the logical page number is absent from the correlation table, the machine further comprising:
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first means for activating a function that introduces the logical page number with a correlation to a physical page number in the correlation table following the exception caused by an absence of valid input containing the logical page number in the correlation table, and second means for replacing the first means by third means for activating a function (Trace); and
wherein the activating of the function (Trace) is called from within the task having the exception and executed by the one or more processors. - View Dependent Claims (17, 18, 19, 20)
means for locating the logical page number in said effective address;
means for searching the correlation table for the logical page number; and
means for performing the following steps if the logical page number is not found in said correlation table;
(a) deriving a physical page number in said effective address;
(b) searching a second correlation table for said physical page number;
(c) determining whether said second correlation table stores the logical page number in relation to said physical page number; and
(d) modifying the correlation table to store said physical page number in association with the logical page number based on an outcome of said determining step.
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Specification