Fault resilient/fault tolerant computing

• US 6,473,869 B2
• Filed: 08/10/2001
• Issued: 10/29/2002
• Est. Priority Date: 11/14/1997
• Status: Expired due to Fees

• Current Assignee: Marathon Technologies Corporation (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Marathon Technologies Corporation (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: Bissett, Thomas D., Muench, Erik, Leveille, Paul A.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/925,487
• Publication Number:
  US 20020026604A1
• Time in Patent Office: 445 Days
• Field of Search: 714/12, 714/9, 714/11, 714/10, 714/23, 712/200, 712/229, 712/214, 711/100, 711/106, 709/248, 709/400, 710/22, 710/267, 713/501, 713/600, 703/23, 365/222
• US Class Current: 714/12
• CPC Class Codes: G06F 11/1633 using mutual exchange of the output between the redundant processing components
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/165 with continued operation after detection of the error
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 11/1691 using a quantum

Abstract

A fault tolerant/fault resilient computer system includes at least two compute elements connected to at least one controller. Each compute element has clocks that operate asynchronously to clocks of the other compute elements. The compute elements operate in a first mode in which the compute elements each execute a first stream of instructions in emulated clock lockstep, and in a second mode in which the compute elements each execute a second stream of instructions in instruction lockstep. Each compute element may be a multi-processor compute element.

Claims

1. A fault tolerant/fault resilient computer system, comprising:

at least two compute elements; and

at least one controller connected to the at least two compute elements;

wherein;

each of the compute elements has clocks that operate asynchronously to clocks of the other compute elements,

the compute elements each execute a stream of instructions,

upon issuing an I/O request instruction from the stream of instructions, each compute element enters a halted state, and

each compute element is removed from the halted state by an interrupt generated upon completion of the I/O request instruction.

2. The system of claim 1, wherein timing of the interrupt is controlled such that operation of the compute elements is synchronized upon generation of the interrupt.

3. The system of claim 1, wherein each compute element executes an alignment process in response to the interrupt, the alignment process serving to synchronize operation of the compute elements.

4. The computer system of claim 1, wherein the at least two compute elements each comprise a multi-processor compute element.

5. The computer system of claim 4, wherein the at least two compute elements each comprise a symmetric multi-processor (SMP) compute element.

6. The computer system of claim 4, wherein each compute element is implemented using an industry standard motherboard.

7. The computer system of claim 1, wherein each compute element comprises a processor, memory, and a connection to the controller.

8. The computer system of claim 7, wherein each compute element is configured so that refresh operations associated with the memory are synchronized with execution of operations by the processor.

9. The computer system of claim 7, wherein the system is configured to synchronize compute elements by:

copying contents of the memory of a first compute element to the memory of a second compute element; and

resetting the processors of the first and second compute elements without affecting the memories of the compute elements.

10. The computer system of claim 1, wherein the system is configured to redirect I/O operations by the compute elements to the controller.

11. The computer system of claim 1, further comprising a second controller connected to the first controller and to the at least two compute elements.

12. The computer system of claim 11, wherein the first controller and a first one of the compute elements are located in a first location and the second controller and a second one of the compute elements are located in a second location, and further comprising a communications link connecting the first controller to the second controller, the first controller to the second one of the compute elements, and the second controller to the first one of the compute elements.

13. The computer system of claim 12, wherein the first location is spaced from the second location by more than 5 meters.

14. The computer system of claim 12, wherein the first location is spaced from the second location by more than 100 meters.