Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid

• US 6,473,883 B1
• Filed: 11/29/2001
• Issued: 10/29/2002
• Est. Priority Date: 11/29/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Thorp, Tyler, Bobba, Sudhakar
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/997,437
• Time in Patent Office: 334 Days
• Field of Search: 356/608, 716/2, 716/10, 716/11, 716/12, 716/13
• US Class Current: 716/113
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method for improving integrated circuit by using a patterned bump layout on a layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

Claims

1. A method for designing an integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the method comprising:

defining a desired angle, wherein the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, wherein the first and second bumps reside on the first metal bar, and wherein the reference bump resides on the second metal bar; and

using the desired angle to position the first metal bar, the first bump, and the second bump on the integrated circuit.

2. The method of claim 1, wherein using the desired angle to position the first metal bar, the first bump, and the second bump creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising:

repeating the bump structure across the top metal layer.

3. The method of claim 1, wherein using the desired angle to position the first metal bar, the first bump, and the second bump creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising:

repeating the bump structure across a portion of the top metal layer.

4. The method of claim 1, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.

5. The method of claim 1, further comprising:

determining a value of the desired angle prior to positioning the first metal bar, the first bump, and the second bump on the integrated circuit.

6. The method of claim 5, wherein determining the value of the desired angle is dependent upon at least one selected from the group consisting of:

a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, desired signal track availability.

7. A method for designing an integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the method comprising:

defining a desired angle, wherein the desired angle represents an angle formed between a line from a reference bump to a first bump and a line from the reference bump to a second bump, wherein the first and second bumps reside on the first metal bar, and wherein the reference bump resides on the second metal bar; and

using the desired angle to position the first metal bar and the second metal bar on the integrated circuit.

8. The method of claim 7, wherein using the desired angle to position the first metal bar and the second metal bar on the integrated circuit creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising:

repeating the bump structure across the top metal layer.

9. The method of claim 7, wherein using the desired angle to position the first metal bar and the second metal bar on the integrated circuit creates a particular bump structure among the first bump, the second bump, and the reference bump, the method further comprising:

repeating the bump structure across a portion of the top metal layer.

10. The method of claim 7, wherein the first metal bar is operatively connected to a voltage source, and wherein the second metal bar is operatively connected to ground.

11. The method of claim 7, further comprising:

determining a value of the desired angle prior to positioning the first metal bar and the second metal bar on the integrated circuit.

12. The method of claim 11, wherein determining the value the desired angle is dependent upon at least one selected from the group consisting of:

a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, desired signal track availability.

13. A computer system, comprising:

a processor;

a memory; and

instructions, residing in the memory and executable on the processor, for determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump.

14. The computer system of claim 13, wherein the reference bumps resides on a first metal bar of a metal layer of an integrated circuit, and wherein the first and second bumps reside on a second metal bar of the metal layer.

15. The computer system of claim 13, wherein determining the value of the angle is dependent on a desired metal layer property comprising at least one selected from the group consisting of:

a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the metal layer, desired signal track availability.

16. The computer system of claim 15, further comprising:

determining a metal layer design based on the desired metal layer property.

17. A computer-readable medium having instructions therein executable by processing, the instructions for:

inputting a desired metal layer property; and

determining a value of an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump based on the desired metal layer property,

wherein the reference bump resides on a first metal bar, and wherein the first and second bumps reside on a second metal bar.

18. The computer-readable medium of claim 17, wherein the value of the angle is used to create a particular bump placement among the first bump, the second bump, and the reference bump.

19. The computer-readable medium of claim 18, wherein the bump placement is repeated across a metal layer of an integrated circuit.

20. The computer-readable medium of claim 18, wherein the bump placement is repeated across a portion of a metal layer of an integrated circuit.