Method of making a scalable two transistor memory device
First Claim
1. A method of manufacturing a scalable two-transistor memory cell array having three control lines including bit lines, data lines and word lines, each memory cell having a bottom transistor and a top transistor in a stacked configuration, comprising the steps of:
- providing a substrate having an x-axis and a y-axis;
depositing a first gate dielectric layer on the substrate;
depositing a first conductive layer on the first gate dielectric layer to form a storage node layer;
depositing alternating layers of a low band gap semiconductor layer and a large band gap insulator layer to form a multiple tunnel junction barrier on the storage node layer;
depositing a second conductive layer to form a source layer of the top transistor;
etching the second conductive layer, the multiple tunnel junction layer, the first conductive layer and the first gate dielectric layer into the substrate to form a plurality of island-type trench isolation regions using a photolithographic process;
depositing a first insulating layer over the substrate to fill the trench regions;
depositing a third conductive layer over the first insulating layer and the second conductive layer to form data lines;
etching the third conductive layer, the second conductive layer, multiple tunnel junction layer, the first conductive layer and the first gate dielectric layer until the substrate surface is exposed, to form grooves in a direction parallel with y-axis in between the island-type filled trench isolation regions using a photolithographic process;
implanting impurities in the exposed substrate to form the source/drain extension regions of the bottom transistor in the grooves formed in a direction parallel with the y-axis;
forming bit lines in the grooves formed in a direction parallel with the y-axis;
depositing a second insulating layer over the cell array and etched grooves in a direction parallel with the y-axis;
forming a photoresist pattern defining control gate lines over the second insulating layer;
performing an etching process to etch away the second insulating layer between and on top of adjacent memory cells in a direction parallel with the x-axis;
removing the photoresist pattern;
depositing second gate dielectric layers on the sidewalls of the multiple tunnel junction barrier structure;
depositing fourth conductive layer over the entire surface of the array; and
forming the word lines by chemical mechanical polishing (CMP) or etching of the fourth conductive layer.
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Abstract
A method of fabricating a multiple tunnel junction Scalable Two-Transistor Memory (STTM) cell array with a unit cell area as low as 4F2, F representing the minimum feature dimension, which usually is the width and also the spacing of the data lines or the write (or word or control gate) lines, wherein process sequence and conditions are designed to offer wide flexibility in material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence. The processing of memory cell devices is made compatible with peripheral CMOS devices so that the devices in both areas can be made simultaneously, thereby decreasing the total number of processing steps. Insulator filled trenches around the device regions, source/drain and the gate regions of the peripheral devices are formed simultaneously with the corresponding regions of the memory cell devices.
164 Citations
61 Claims
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1. A method of manufacturing a scalable two-transistor memory cell array having three control lines including bit lines, data lines and word lines, each memory cell having a bottom transistor and a top transistor in a stacked configuration, comprising the steps of:
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providing a substrate having an x-axis and a y-axis;
depositing a first gate dielectric layer on the substrate;
depositing a first conductive layer on the first gate dielectric layer to form a storage node layer;
depositing alternating layers of a low band gap semiconductor layer and a large band gap insulator layer to form a multiple tunnel junction barrier on the storage node layer;
depositing a second conductive layer to form a source layer of the top transistor;
etching the second conductive layer, the multiple tunnel junction layer, the first conductive layer and the first gate dielectric layer into the substrate to form a plurality of island-type trench isolation regions using a photolithographic process;
depositing a first insulating layer over the substrate to fill the trench regions;
depositing a third conductive layer over the first insulating layer and the second conductive layer to form data lines;
etching the third conductive layer, the second conductive layer, multiple tunnel junction layer, the first conductive layer and the first gate dielectric layer until the substrate surface is exposed, to form grooves in a direction parallel with y-axis in between the island-type filled trench isolation regions using a photolithographic process;
implanting impurities in the exposed substrate to form the source/drain extension regions of the bottom transistor in the grooves formed in a direction parallel with the y-axis;
forming bit lines in the grooves formed in a direction parallel with the y-axis;
depositing a second insulating layer over the cell array and etched grooves in a direction parallel with the y-axis;
forming a photoresist pattern defining control gate lines over the second insulating layer;
performing an etching process to etch away the second insulating layer between and on top of adjacent memory cells in a direction parallel with the x-axis;
removing the photoresist pattern;
depositing second gate dielectric layers on the sidewalls of the multiple tunnel junction barrier structure;
depositing fourth conductive layer over the entire surface of the array; and
forming the word lines by chemical mechanical polishing (CMP) or etching of the fourth conductive layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 57, 58, 59, 61)
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52. A method of manufacturing peripheral circuitry CMOS devices of a scalable two-transistor memory, comprising the steps of:
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forming a gate dielectric layer, a first conductive layer, alternating layers of a multiple tunnel junction (MTJ) barrier, a second conductive layer and a CMP stopping layer at the same time these layers are formed for a memory device array;
selectively removing the CMP stopping layer, the second conductive layer and the MTJ barrier layers all on top of the peripheral CMOS device area leaving the first conductive layer and the gate dielectric layer;
forming a conductive layer on an entire surface of the substrate where the CMP stopping layer, the second conductive layer and the MTJ barrier layers are selectively removed;
patterning the conductive layer, the CMP stopping layer, the second conductive layer, the MTJ barrier layers and the first conductive layer to form data lines in the memory device array and a peripheral CMOS device gate structure in the peripheral CMOS device area; and
forming source/drain regions of the peripheral CMOS device. - View Dependent Claims (53, 54, 55, 56, 60)
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Specification