Method of forming a double gate transistor having an epitaxial silicon/germanium channel region

• US 6,475,869 B1
• Filed: 02/26/2001
• Issued: 11/05/2002
• Est. Priority Date: 02/26/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): Chen, Jack
• Application Number:
  US09/793,055
• Time in Patent Office: 617 Days
• Field of Search: 438/149, 438/151, 438/156, 438/157, 438/164, 438/173, 438/176, 438/197, 438/182, 438/212, 438/222, 438/267, 438/268, 438/269, 438/286, 438/299, 438/300, 438/303, 438/304, 438/479, 438/574, 438/585, 438/588, 438/590, 438/592, 438/595
• US Class Current: 438/303
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Claims

1. A method of manufacturing an integrated circuit on a substrate, the method comprising:

providing a fin area in the substrate;

narrowing a width of the fin area by growing a sacrificial material on first sidewalls of the fin area and subsequently removing the sacrificial material to form second sidewalls on the fin area;

providing silicon-germanium material on the second sidewalls of the fin area;

providing a dielectric layer over the slicon-germanium material; and

providing a gate conductor over the dielectric layer.

2. The method of claim 1, further comprising:

before the providing a fin area, providing a cap layer above the substrate.

3. The method of claim 2, wherein the cap layer is silicon nitride.

4. The method of claim 2, wherein the cap layer includes ends extending above the silicon-germanium material.

5. The method of claim 3, wherein the dielectric layer is provided above the cap layer.

6. The method of claim 1, wherein the silicon-germanium material is laterally grown by epitaxy.

7. The method of claim 1, wherein the substrate includes a buried oxide layer and a single crystalline silicon thin film.

8. The method of claim 1, wherein the gate conductor surrounds at least three sides of the fin area.

9. The method of claim 1, wherein the dielectric layer is a silicon nitride.

10. The method of claim 1, wherein the silicon-germanium material is undoped.

11. A method of manufacturing an integrated circuit on a substrate, the method comprising:

providing a fin area in the substrate, the fin area having sidewalls;

providing silicon-germanium material on sidewalls of the fin area;

providing a sacrificial oxide on the sidewalls of the fin area and removing the sacrificial oxide before providing the silicon-germanium material on the sidewalls;

providing a dielectric layer over the silicon-germanium material; and

providing a gate conductor over the dielectric layer.

12. The method of claim 11, wherein the gate conductor is disposed above the fin area, the gate conductor being above a top side and two lateral sides of the fin area.

13. The method of claim 11, further comprising:

providing a cap layer above the top side of the fin area.

14. The method of claim 11, wherein a source region and a drain region are disposed on ends of the fin area and the gate conductor is disposed over a middle portion of the fin area.

15. The method of claim 11, wherein the silicon-germanium material is part of a channel region.

16. The material of claim 15, wherein the silicon-germanium material is 50-100 Å

thick.

17. The method of claim 16, further comprising:

providing a cap layer, the cap layer being 100-200 Å

wider than the fin area at the channel region.

18. A process of forming a transistor having a semiconductor-germanium channel region, the process comprising:

forming an island of semiconductor material on a substrate, the island having a cap layer;

growing oxide material on sidewalls of the island;

removing the oxide material;

forming a single crystalline semiconductor-germanium layer on the sidewalls of the island; and

providing a gate structure over at least a portion of the island.

19. The process of claim 18, further comprising:

providing a source region and a drain region on ends of the island, the ends being separated by the gate structure.

20. The process of claim 19, wherein the removing is done by wet chemical etching.