Passive multiplexor test structure for integrated circuit manufacturing

• US 6,475,871 B1
• Filed: 11/17/2000
• Issued: 11/05/2002
• Est. Priority Date: 11/18/1999
• Status: Active Grant

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Hess, Christopher, Stine, Brian E., Weiland, Larg H.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US09/715,851
• Time in Patent Office: 718 Days
• Field of Search: 257/48, 356/230.06, 438/18, 365/201
• US Class Current: 438/381
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.

Claims

1. A method for analyzing failures due to fabrication induced defects in integrated circuits comprising the steps of:

a) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto; and

b) providing a plurality of passive test structures, each associated with a respective first line and a respective second line, each test structure electrically connected between a first line and a second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models.

2. The method in accordance with claim 1 wherein at least one of the test structures comprises a serial via chain.

3. The method in accordance with claim 1 wherein at least one of the test structures comprises a serial contact chain.

4. The method in accordance with claim 1 wherein at least one of the test structures comprises a poly/contact/metal 1 structure.

5. The method in accordance with claim 1 wherein at least one of the test structures comprises a active/contact/mretal 1 structure.

6. The method in accordance with claim 1 wherein at least one of the test structures comprises a metal, poly, or active line for detecting metal, poly, or active opens.

7. The method in accordance with claim 1 wherein at least one of the test structures comprises a transistor for detecting transistor opens.

8. The method in accordance with claim 1 wherein step (b) includes varying attribute values, so that two or more of the plurality of test structures have respectively different attribute values for at least one of the following:

1) metal 1 border x and y directions;

2) spacing of metal 2 neighbor to via chain;

3) misalignment of via to metal 1, x and y directions;

4) misalignment of via to metal 2, x and y directions;

5) spacing of metal 1 neighbor to via chain;

6) spacing of via to nearest via;

7) metal 2 border x and y directions;

8) via hole size;

9) metal 2 runner length;

10) metal 1 neighbor line width perpendicular to via chain;

11) metal 2 neighbor line width parallel to via chain;

12) metal 2 neighbor line width perpendicular to via chain;

13) metal 2 runner length; and

14) metal 1 neighbor line width perpendicular to via chain.

21. The method of claim 1, wherein the first lines, second lines, first line probe pads, second line probe pads and plurality of test structures are formed in a short flow test vehicle.

9. A method for analyzing failures due to fabrication induced defects in integrated circuits comprising:

a) providing a source of electrical current, said current source having a first electrical potential of a first magnitude and a second electrical potential of a second magnitude which differs from the first magnitude by a predetermined amount;

b) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto, all first line probe pads being electrically connected to the first potential of said current source and each second line probe pad being selectively, individually electrically connectable to the second potential of said current source;

c) providing test structures associated with said first and second lines, each test structure electrically connected between a respective first line and a respective second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models; and

d) electrically connecting a current measuring device to each first line for measuring the current through the test structure associated with said first line.

10. The method in accordance with claim 9 wherein at least one of the test structures comprises a serial via chain.

11. The method in accordance with claim 9 wherein at least one of the test structures comprises a serial contact chain.

12. The method in accordance with claim 9 wherein at least one of the test structures comprises a poly/contact/metal 1 structure.

13. The method in accordance with claim 9 wherein at least one of the test structures comprises a active/contact/metal 1 structure.

14. The method in accordance with claim 9 wherein at least one of the test structures comprises a metal, poly, or active line for detecting metal, poly, or active opens.

15. The method in accordance with claim 9 wherein at least one of the test structures comprises a transistor for detecting transistor opens.

16. The method in accordance with claim 9 wherein step (c) includes varying attribute values so that two or more of the plurality of test structures have respectively different attribute values for at least one of the following:

1) metal 1 border x and y directions;

2) spacing of metal 2 neighbor to via chain;

3) misalignment of via to metal 1, x and y directions;

4) misalignment of via to metal 2, x and y directions;

5) spacing of metal 1 neighbor to via chain;

6) spacing of via to nearest via;

7) metal 2 border x and y directions;

8) via hole size;

9) metal 2 runner length;

10) metal 1 neighbor line width perpendicular to via chain;

11) metal 2 neighbor line width parallel to via chain;

12) metal 2 neighbor line width perpendicular to via chain;

13) metal 2 runner length; and

14) metal 1 neighbor line width perpendicular to via chain.

22. The method of claim 9, wherein the first lines, second lines, first line probe pads, second line probe pads and plurality of test structures are formed in a short flow test vehicle.

17. A method for analyzing failures due to fabrication induced defects in integrated circuits comprising the steps of:

a) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto; and

b) providing a plurality of test structures, each associated with a respective first line and a respective second line, each test structure electrically connected between a first line and a second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models, wherein two or more of the plurality of test structures have respectively different attribute values for the at least one variable attribute, wherein step (b) includes varying the value of at least one of the following;

1) metal box 1 border x and y directions;

2) spacing of metal 2 neighbor to via chain;

3) misalignment of via to metal 1, x and y directions;

4) misalignment of via to metal 2, x and y directions;

5) spacing of metal 1 neighbor to via chain;

6) spacing of via to nearest via;

7) metal 2 border x and y directions;

8) via hole size;

9) metal 2 runner length;

10) metal 1 neighbor line width perpendicular to via chain;

11) metal 2 neighbor line width parallel to via chain;

12) metal 2 neighbor line width perpendicular to via chain;

13) metal 2 runner length; and

14) metal 1 neighbor line width perpendicular to via chain.

18. The method of claim 17, wherein step (b) includes varying the attribute values of two or more attributes so that each varied attribute has two or more values, whereby the plurality of test structure include four or more different combinations of attribute values.

19. The method of claim 18, wherein step (b) includes varying the values of two or more of the following attributes:

1) metal 1 border x and y directions;

2) spacing of metal 2 neighbor to via chain;

3) misalignment of via to metal 1, x and y directions;

4) misalignment of via to metal 2, x and y directions;

5) spacing of metal 1 neighbor to via chain;

6) spacing of via to nearest via;

7) metal 2 border x and y directions;

8) via hole size;

9) metal 2 runner length;

10) metal 1 neighbor line width perpendicular to via chain;

11) metal 2 neighbor line width parallel to via chain;

12) metal 2 neighbor line width perpendicular to via chain;

13) metal 2 runner length; and

14) metal 1 neighbor line width perpendicular to via chain.

20. The method of claim 18, further comprising:

testing the plurality of test structures; and

identifying the impact of each attribute on the yield, based on the testing.

23. The method of claim 17, wherein the first lines, second lines, first line probe pads, second line probe pads and plurality of test structures are formed in a short flow test vehicle.