Damascene NiSi metal gate high-k transistor

• US 6,475,874 B2
• Filed: 12/07/2000
• Issued: 11/05/2002
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Xiang, Qi, Besser, Paul R., Buynoski, Matthew S., King, Paul L., Paton, Eric N., Foster, John C.
• Primary Examiner(s): EVERHART, CARIDAD
• Application Number:
  US09/731,031
• Publication Number:
  US 20020102848A1
• Time in Patent Office: 698 Days
• Field of Search: 438/396, 438/299, 438/655, 438/197, 438/585, 438/595, 438/305, 438/392, 438/301, 438/303, 438/592
• US Class Current: 438/396
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.

Claims

1. A method of forming a semiconductor structure comprising the steps of:

forming a precursor having a substrate with active regions separated by a channel, and a temporary gate over the channel and between dielectric structures;

removing the temporary gate to form a recess with a bottom and sidewalls between the dielectric structures;

depositing a high dielectric constant (high K) gate dielectric layer in the recess on the bottom and sidewalls;

depositing amorphous silicon over the semiconductor including the recess;

removing the amorphous silicon except for a portion in the recess;

depositing low temperature silicidation metal over the semiconductor structure wherein the low temperature silicidation metal is nickel;

annealing to cause the low temperature silicidation metal and the portion of the amorphous silicon in the recess to interact to form a self-aligned low temperature metal silicide gate electrode; and

removing the low temperature silicidation metal remaining unreacted after the annealing.

2. The method of claim 1, wherein a thickness of the high K gate dielectric layer is between approximately 50 Å

and approximately 200 Å

.

3. The method of claim 1, wherein the amorphous silicon is formed by a lower temperature chemical vapor deposition (CVD) at a temperature between approximately 500°

C. and approximately 600°

C.

4. The method of claim 1, wherein the amorphous silicon is removed by a chemical mechanical polishing (CMP).

5. The method of claim 1, wherein the annealing is performed by a rapid thermal annealing at a temperature between approximately 400°

C. and approximately 600°

C. for a period of between approximately 30 seconds and approximately 60 seconds.

6. The method of claim 1, wherein further processing of the semiconductor structure is maintained below a temperature sufficient to prevent a substantial interaction between the high k gate dielectric layer and the substrate.

7. The method of claim 6, wherein the temperature is approximately 700°

C.

8. The method of claim 1, wherein the remaining low temperature silicidation metal is removed by an etchant having a high selectivity between the low temperature silicidation metal and the low temperature metal silicide gate.

9. The method of claim 8, wherein the etchant is sulfuric acid, nitric acid or hydrogen peroxide.

10. The method of claim 1, wherein the dielectric structures are an interlayer dielectric.

11. A method of implementing a high k gate dielectric layer in a semiconductor structure comprising the steps of:

forming active regions with a channel therebetween on a main surface of a semiconductor substrate;

forming high temperature silicide on the active regions;

forming a temporary gate over the channel between dielectric structures;

removing the temporary gate to form a recess with a bottom and sidewalls between the dielectric structures;

depositing a high dielectric constant (high k) gate dielectric in the recess;

depositing amorphous silicon over the dielectric structure and the high k gate dielectric in the recess;

removing the amorphous silicon except for a portion in the recess;

depositing a low temperature silicidation metal on the amorphous silicon wherein the low temperature silicidation metal is nickel;

annealing to cause the low temperature silicidation metal and the portion of the amorphous silicon to interact to form a self-aligned low temperature metal silicide gate on the high k gate dielectric in the recess; and

removing the low temperature silicidation metal remaining unreacted after the annealing.

12. The method of claim 11, wherein the active regions are formed by ion implanting an impurity and annealing at a temperature higher than approximately 700°

C.

13. The method of claim 11, wherein the high temperature silicide is formed at a processing temperature higher than approximately 700°

C.

14. The method of claim 11, wherein the annealing is performed at a temperature lower than approximately 700°

C.