Thin film transistor for liquid crystal display

• US 6,476,418 B1
• Filed: 06/30/1998
• Issued: 11/05/2002
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Gold Charm Limited (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: NEC Corporation
• Inventors: Sukegawa, Osamu, Shiga, Shunsuke
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US09/108,093
• Time in Patent Office: 1,589 Days
• Field of Search: 257/59, 257/72
• US Class Current: 257/72
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

In a TFT (Thin Film Transistor) of the present invention applicable to an LCD (Liquid Crystal Display) includes a gate electrode, a gate insulation film, an island-like semiconductor layer, a drain electrode and a source electrode sequentially laminated on a transparent insulative substrate. A part of the semiconductor layer above the gate electrode in the direction of channel length has a smaller dimension than the other part in the direction of channel width. With this configuration, the TFT reduces a light OFF current while preventing a light ON current from being reduced.

Claims

1. In a TFT for an LCD and having a gate electrode, a gate insulation film, an island-like semiconductor layer, a drain electrode and a source electrode sequentially laminated on a transparent insulative substrate, said semiconductor layer has a dimension, in a direction of channel width and in a region between said source and drain electrodes which is smaller than a dimension of said semiconductor layer in said direction of channel width outside said region, wherein said gate electrode extends past all portions of said semiconductor layer in the direction of channel width.

2. A TFT as claimed in claim 1, wherein said first portion of said semiconductor layer is formed by notching opposite side edges of said semiconductor layer in the direction of channel width.

3. A TFT as claimed in claim 2, wherein said semiconductor layer includes a plurality of regions adjoining both said drain electrode and said source electrode and not shielded by said gate electrode.

4. A TFT as claimed in claim 3, wherein said plurality of regions face each other at diagonal positions on said drain electrode and said source electrode.

5. A TFT as claimed in claim 1, wherein said semiconductor layer includes a plurality of regions adjoining both said drain electrode and said source electrode and not shielded by said gate electrode.

6. A TFT as claimed in claim 5, wherein said plurality of regions face each other at diagonal positions on said drain electrode and said source electrode.

7. A TFT as claimed in claim 1, wherein said first portion of said semiconductor layer is formed by notching opposite side edges of said semiconductor layer in the direction of channel width.

8. A TFT as claimed in claim 7, wherein said semiconductor layer includes a plurality of regions adjoining both said drain electrode and said source electrode and not shielded by said gate electrode.

9. A TFT as claimed in claim 8, wherein said plurality of regions face each other at diagonal positions on said drain electrode and said source electrode.

10. A TFT as claimed in claim 1, wherein said semiconductor layer includes a plurality of regions adjoining both said drain electrode and said source electrode and not shielded by said gate electrode.

11. A TFT as claimed in claim 10, wherein said plurality of regions face each other at diagonal positions on said drain electrode and said source electrode.

12. In a TFT for an LCD and having a gate electrode, a gate insulation film, an island-like semiconductor layer, a drain electrode and a source electrode sequentially laminated on a transparent insulative substrate, said semiconductor layer has a dimension, in a direction of channel width and in a region between said source and drain electrodes which is smaller than a dimension of said semiconductor layer in said direction of channel width outside said region, wherein said gate electrode extends past all portions of said semiconductor layer in the direction of channel width and wherein said semiconductor layer has a plurality of portions not shielded by said gate electrode in the vicinity of said drain electrode and said source electrode.

15. A TFT as claimed in claim 12, wherein said plurality of regions face each other at diagonal positions on said drain electrode and said source electrode.

13. A TFT as claimed in 12, wherein the dimension of said first portion of said semiconductor layer is substantially equal to or greater than a dimension of each of said drain electrode and said source electrode in the direction of channel width.

14. A TFT as claimed in claim 13, wherein said first portion of said semiconductor layer is formed by notching opposite side edges of said semiconductor layer in the direction of channel width.

16. In a TFT for an LCD and having a gate electrode, a gate insulation film, and island-like semiconductor layer, a drain electrode and a source electrode sequentially laminated on a transparent insulative substrate, said semiconductor layer has a dimension, in a direction of channel width and in a region between said source and drain electrodes which is smaller than a dimension of said semiconductor layer in said direction of channel width outside said region, wherein said gate electrode extends past all portions of said semiconductor layer in the direction of channel width and wherein said semiconductor layer has a plurality of a portions not shielded by said gate electrode in the vicinity of said drain electrode and said source electrode, and wherein said plurality of portions not shielded by said gate electrode are at diagonal positions relative to said drain electrode and said source electrode.

17. A TFT as claimed in 16, wherein the dimension of said first portion of said semiconductor layer is substantially equal to or greater than a dimension of each of said drain electrode and said source electrode in the direction of channel width.

18. A TFT as claimed in claim 17, wherein said first portion of said semiconductor layer is formed by notching opposite side edges of said semiconductor layer in the direction of channel width.