Pseudo-Schottky diode

• US 6,476,442 B1
• Filed: 03/09/1998
• Issued: 11/05/2002
• Est. Priority Date: 05/15/1996
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Blattner, Robert, Williams, Richard K.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/037,557
• Time in Patent Office: 1,702 Days
• Field of Search: 257/327-335, 257/355, 257/356, 257/358, 257/336
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An N-channel MOSFET is fabricated with its source, body and gate connected together and biased at a positive voltage with respect to its drain. The resulting two-terminal device functions generally in the manner of a diode but has a significantly lower turn-on voltage than a conventional PN diode. The device is therefore referred to as a “pseudo-Schottky mode”. Pseudo-Schottky diodes have numerous uses, but they are particularly useful when connected to shunt current from a conventional PN diode or MOSFET and thereby prevent such conditions as snapback and latchup which can result from the storage of minority carriers in a forward-biased PN junction. Also, because the pseudo-Schottky diode is a majority carrier device, the diode recovery time, amount of stored charge, and peak reverse current are much lower than in a conventional PN diode.

Claims

1. A combination of a MOSFET and a pseudo-Schottky diode comprising:

a semiconductor chip;

a first gate electrically insulated from a second gate, said first gate being separated from said semiconductor chip by a first insulating layer, said second gate being separated from said semiconductor chip by a second insulating layer;

said semiconductor chip comprising;

a source region of a first conductivity type comprising a first portion adjacent said first insulating layer and a second portion adjacent said second insulating layer;

a body region of a second conductivity type comprising a first portion adjacent said first insulating layer and a second portion adjacent said second insulating layer;

a drain region of said first conductivity type adjacent said first and second portions of said body region and said first and second insulating layers,

wherein said second portion of said source region and said second portion of said body region are shorted together, and wherein said first portion of said source region, said first portion of said body region and said first gate are shorted together.

2. The combination of claim 1 further comprising a metal layer in electrical contact with said source and body regions.

3. An integrated circuit chip comprising:

a semiconductor device comprising;

a first region of a first conductivity type; and

a second region of a second conductivity type, said first region and said second region being adjacent to each other and being separated by a first PN junction; and

a pseudo-Schottky diode comprising

a source region of said second conductivity type;

a body region of said first conductivity type adjacent said source region;

a drain region of said second conductivity type adjacent said body region; and

a gate separated by an insulating layer from a channel region of said body region,

wherein said source region, said body region, said gate and said first region are shorted together and wherein said drain region and said second region are shorted together.

4. The integrated circuit chip of claim 3 wherein said source region and said drain region are formed at a top surface of said integrated circuit chip, said channel region being located between said source region and said drain region.

5. The integrated circuit chip of claim 3 wherein said source region and said body region are adjacent a top side of said integrated circuit and said drain region is adjacent a back side of said integrated circuit chip.

6. The integrated circuit chip of claim 3 wherein a thickness of said insulating layer is in the range of 400 Å

to 1000 Å

.

7. The integrated circuit chip of claim 3 wherein a portion of said channel region contains an implant of dopant for adjusting a threshold voltage of said device.

8. The integrated circuit chip of claim 7 wherein a portion of said body contains a retrograde dopant implant.

9. The integrated circuit chip of claim 3 wherein the semiconductor device is a PN diode.

10. The integrated circuit chip of claim 9 wherein said diode has an anode and a cathode and wherein said source region, said body region, and said gate are shorted to one of said anode and said cathode and said drain region is shorted to the other of said anode and said cathode.

11. The integrated circuit chip of claim 3 wherein the semiconductor device is a MOSFET, said first region comprising a second body region and said second region comprising said drain region, said MOSFET further comprising a second source region of said second conductivity type and a second gate, said second source and body regions being shorted together.