MOSgated device with trench structure and remote contact and process for its manufacture

• US 6,476,443 B1
• Filed: 10/13/1999
• Issued: 11/05/2002
• Est. Priority Date: 10/14/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Kang, Donghee
• Application Number:
  US09/416,796
• Time in Patent Office: 1,119 Days
• Field of Search: 257/329, 257/330, 257/327, 257/328, 257/397, 257/331, 257/332, 257/339, 257/341, 257/342, 257/5, 257/334, 438/212, 438/259, 438/268, 438/270, 438/271, 438/587, 438/588, 438/589
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with a single common layer of conductive polysilicon which extends into each trench and overlies the silicon surface which connects adjacent trenches. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The trench is from 0.2 to 0.25 microns deeper than the channel region. The device has a very low figure of merit and is useful especially in low voltage circuits.

Claims

1. A MOSgated device comprising:

a semiconductor substrate of one of the conductivity types and having an upper planar surface;

a channel diffusion region of the other of the conductivity types which extends into said upper planar surface of said substrate and to a first depth below said surface;

a source diffusion of said one of the conductivity types which extends into said substrate to a second depth which is less than said first depth;

a plurality of rows of spaced, longitudinally parallel trenches formed into said substrate and into said upper planar surface to a third depth below said substrate surface which is greater than said first depth, said rows being separated by untrenched areas not lateral to said longitudinal sides of said trenches;

an insulation gate layer formed on the walls of said plurality of trenches at least in the areas between said first and second depths;

a conductive gate material disposed atop said insulation gate layer and within the interior of said trench;

a gate electrode connected to said conductive gate;

and a drain contact connected to said substrate; and

at least one source contact disposed in an untrenched area and connected to said source diffusion region.

2. The device of claim 1, wherein said spaced trenches are coextensive with one another.

3. The device of claim 1 wherein said trenches have a depth of about 1.8 microns.

4. The device of claim 1 wherein said third depth is about 0.2 to 0.25 microns deeper than said first depth.

5. The device of claim 3 wherein said third depth is about 0.2 to 0.25 microns deeper than said first depth.

6. The device of claim 1 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

7. The device of claim 3 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

8. The device of claim 4 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

9. The device of claim 1 wherein said gate insulation is an oxide layer having a thickness greater than about 200 Å

and which fully covers the interior of each of said trenches and wherein said conductive gate is a continuous layer of polysilicon which completely fills each of said trenches and is insulated from said substrate.

10. The device of claim 1 wherein said source contact is further connected to said channel region as well as said source region.

11. The device of claim 3 wherein said source contact location is disposed between said spaced rows of trenches.

12. The device of claim 11 wherein said trenches have a depth of about 1.8 microns.

13. The device of claim 12 wherein said third depth is about 0.2 to 0.25 microns deeper than said first depth.

14. The device of claim 11 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

15. The device of claim 12 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

16. The device of claim 13 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

17. The device of claim 2 wherein said gate insulation is an oxide layer having a thickness greater than about 200 Å

and which fully covers the interior of each of said trenches and wherein said conductive gate is a continuous layer of polysilicon which completely fills each of said trenches and is insulated from said substrate.

18. The device of claim 3 wherein said gate insulation is an oxide layer having a thickness greater than about 200 Å

and which fully covers the interior of each of said trenches and wherein said conductive gate is a continuous layer of polysilicon which completely fills each of said trenches and is insulated from said substrate.

19. The device of claim 4 wherein said gate insulation is an oxide layer having a thickness greater than about 200 Å

and which fully covers the interior of each of said trenches and wherein said conductive gate is a continuous layer of polysilicon which completely fills each of said trenches and is insulated from said substrate.

20. The device of claim 6 wherein said gate insulation is an oxide layer having a thickness greater than about 200 Å

and which fully covers the interior of each of said trenches and wherein said conductive gate is a continuous layer of polysilicon which completely fills each of said trenches and is insulated from said substrate.

21. The device of claim 11 wherein said source contact is connected to said channel region as well as said source region.

22. The device of claim 21 wherein said trenches have a depth of about 1.8 microns.

23. The device of claim 22 wherein said third depth is about 0.2 to 0.25 microns deeper than said first depth.

24. The device of claim 23 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

25. The device of claim 24 wherein said gate insulation is an oxide layer having a thickness greater than about 200 Å

and which fully covers the interior of each of said trenches and wherein said conductive gate is a continuous layer of polysilicon which completely fills each of said trenches and is insulated from said substrate.

26. The device of claim 6 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

27. The device of claim 7 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

28. The device of claim 8 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

29. The device of claim 14 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

30. The device of claim 15 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

31. The device of claim 16 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

32. The device of claim 20 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

33. The device of claim 21 wherein each of said trenches has a length greater than about 6 microns but less than about 20 microns.

34. In a MOSgated device;

a semiconductor substrate of one of the conductivity types and having an upper surface;

at least first and second invertible vertical channel forming trenches formed through said upper surface and into said substrate for a first depth;

a gate oxide coating the interior walls of said at least first and second trenches;

a channel region of the other conductivity type disposed adjacent to a portion of the length of the walls of said first and second trenches and to a second depth below said upper surface, said second depth being less than said first depth;

a shallow source region which extends from said upper surface and into said substrate for a third depth;

said third depth being less than said second depth;

a continuous conductive polysilicon layer which fills said at least first and second trenches and which is insulated from said substrate; and

a source contact which is fully laterally spaced from the area of said upper surface which is between said at least first and second trenches and connected to at least said source region at a location remote from said first and second trenches;

said source contact extending through said continuous conductive polysilicon layer.

35. The device of claim 34 in which said source contact is also connected to said channel region at said remote location.

36. The device of claim 34 wherein said trenches have a depth of about 1.8 microns.

37. The device of claim 34 wherein said trenches are about 0.2 to 0.25 microns deeper than said channel region.

38. The device of claim 36 wherein said trenches have a depth of about 1.8 microns.

39. The device of claim 37 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

40. The device of claim 36 wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

41. The device of claim 40 wherein said trenches are about 0.2 to 0.25 microns deeper than said channel region.

42. The device of claim 39 in which said source contact is also connected to said channel region at said remote location.

43. The device of claim 41 in which said source contact is also connected to said channel region at said remote location.