MOSgated device with trench structure and remote contact and process for its manufacture
First Claim
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1. A MOSgated device comprising:
- a semiconductor substrate of one of the conductivity types and having an upper planar surface;
a channel diffusion region of the other of the conductivity types which extends into said upper planar surface of said substrate and to a first depth below said surface;
a source diffusion of said one of the conductivity types which extends into said substrate to a second depth which is less than said first depth;
a plurality of rows of spaced, longitudinally parallel trenches formed into said substrate and into said upper planar surface to a third depth below said substrate surface which is greater than said first depth, said rows being separated by untrenched areas not lateral to said longitudinal sides of said trenches;
an insulation gate layer formed on the walls of said plurality of trenches at least in the areas between said first and second depths;
a conductive gate material disposed atop said insulation gate layer and within the interior of said trench;
a gate electrode connected to said conductive gate;
and a drain contact connected to said substrate; and
at least one source contact disposed in an untrenched area and connected to said source diffusion region.
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Abstract
A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with a single common layer of conductive polysilicon which extends into each trench and overlies the silicon surface which connects adjacent trenches. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The trench is from 0.2 to 0.25 microns deeper than the channel region. The device has a very low figure of merit and is useful especially in low voltage circuits.
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Citations
43 Claims
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1. A MOSgated device comprising:
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a semiconductor substrate of one of the conductivity types and having an upper planar surface;
a channel diffusion region of the other of the conductivity types which extends into said upper planar surface of said substrate and to a first depth below said surface;
a source diffusion of said one of the conductivity types which extends into said substrate to a second depth which is less than said first depth;
a plurality of rows of spaced, longitudinally parallel trenches formed into said substrate and into said upper planar surface to a third depth below said substrate surface which is greater than said first depth, said rows being separated by untrenched areas not lateral to said longitudinal sides of said trenches;
an insulation gate layer formed on the walls of said plurality of trenches at least in the areas between said first and second depths;
a conductive gate material disposed atop said insulation gate layer and within the interior of said trench;
a gate electrode connected to said conductive gate;
and a drain contact connected to said substrate; and
at least one source contact disposed in an untrenched area and connected to said source diffusion region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. In a MOSgated device;
- a semiconductor substrate of one of the conductivity types and having an upper surface;
at least first and second invertible vertical channel forming trenches formed through said upper surface and into said substrate for a first depth;
a gate oxide coating the interior walls of said at least first and second trenches;
a channel region of the other conductivity type disposed adjacent to a portion of the length of the walls of said first and second trenches and to a second depth below said upper surface, said second depth being less than said first depth;
a shallow source region which extends from said upper surface and into said substrate for a third depth;
said third depth being less than said second depth;
a continuous conductive polysilicon layer which fills said at least first and second trenches and which is insulated from said substrate; anda source contact which is fully laterally spaced from the area of said upper surface which is between said at least first and second trenches and connected to at least said source region at a location remote from said first and second trenches;
said source contact extending through said continuous conductive polysilicon layer. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43)
- a semiconductor substrate of one of the conductivity types and having an upper surface;
Specification