Semiconductor device and method for fabricating the same

• US 6,476,444 B1
• Filed: 03/17/2000
• Issued: 11/05/2002
• Est. Priority Date: 03/18/1999
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Min, Eung Whan
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/527,263
• Time in Patent Office: 963 Days
• Field of Search: 257/330, 257/331, 257/332, 257/401
• US Class Current: 257/330
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

Semiconductor device and method for fabricating the same, in which a gate electrode is formed buried in a surface of a substrate, for improving device performance. The device includes device isolation layers each buried in a device isolation region of a semiconductor substrate for defining active regions, first gate trenches each with a generally square section formed in a surface of the active region, and second gate trenches each with an elliptical section formed in continuation from the first gate trench. A gate oxide film is formed on surfaces of the first and second gate trenches. Gate electrodes are formed in the first and second trenches having the gate oxide film formed thereon, and source/drain regions are formed in surfaces of the semiconductor substrate on both sides of the gate electrodes insulated from the gate electrodes by the gate oxide film.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a gate trench therein, the gate trench having a first portion with a rectangular cross-section, and a second portion, formed beneath the first portion, having an elliptical cross-section and a width greater than a width of the first portion, the width of said elliptical cross-section being greater than the combined height of said first and second portions;

a gate oxide layer formed on an interior surface of said gate trench;

a gate electrode formed in said gate trench having said gate oxide layer formed on said interior surface thereof; and

source and drain regions formed in said semiconductor substrate adjacent to said gate trench.

2. The device according to claim 1, wherein said source region is formed at a first depth and said drain region is formed at a second depth in said semiconductor substrate, the first depth being deeper than the second depth.

3. The device according to claim 1, wherein said gate trench overlaps said source and drain regions.

4. The device according to claim 1, wherein said second portion overlaps said source and drain regions.

5. The device according to claim 1, comprising an insulating layer formed over said semiconductor substrate including said gate trench having said gate electrode formed therein.

6. The device according to claim 1, wherein said semiconductor substrate includes an active region, said gate trench having said gate electrode formed therein being provided in said active region.

7. The device according to claim 1, wherein said active region is defined by a device isolation layer.

8. A method for fabricating a semiconductor device, comprising:

forming a gate trench in a semiconductor substrate, the gate trench having a first portion with a rectangular cross section, and a second portion, beneath the first portion, having an elliptical cross-section and a width greater than a width of the first portion, the width of said elliptical cross-section being greater than the combined height of said first and second portions;

forming a gate oxide film on an interior surface of the gate trench;

forming a gate electrode in the gate trench; and

forming source and drain regions in the semiconductor substrate adjacent to said gate electrode.

9. The method according to claim 8, wherein forming the first portion comprises dry etching the semiconductor substrate.

10. The method according to claim 8, wherein forming the second portion comprises wet etching the semiconductor substrate.

11. The method according to claim 9, wherein forming the second gate trench comprises wet etching the semiconductor substrate.

12. The method according to claim 8, wherein forming the gate oxide film comprises thermally oxidizing an interior surface of the gate trench.

13. The method according to claim 8, wherein forming the gate electrode comprises depositing polysilicon in the gate trench having the gate oxide film formed therein.

14. The method according to claim 8, wherein forming the source region comprising doping a first region of the semiconductor substrate at first depth and forming the drain region comprises doping a second region of the semiconductor substrate at a second depth, the first depth being deeper than the second depth.

15. The method according to claim 14, the first region is more lightly doped than the second region.

16. The method according to claim 8, further comprising forming a device isolation layer in the semiconductor substrate to define an active region thereon, such that the gate trench having the gate oxide film formed therein and the gate electrode formed in the gate trench are formed in the active region.

17. The method according to claim 8, wherein forming the first portion comprises:

forming an etch mask pattern on the semiconductor substrate so as to leave a portion of the semiconductor substrate exposed;

using the etch mask pattern an etch mask to etch the exposed portion of the semiconductor substrate to form the first portion.

18. The method according to claim 17, wherein forming the etch mask pattern on the semiconductor substrate comprises:

forming a buffer oxide film on the semiconductor substrate;

forming a nitride layer on the buffer oxide film; and

patterning the nitride layer and buffer oxide film to form the etch mask pattern on the semiconductor substrate.

19. The method according to claim 17, comprising dry etching the exposed portion of the semiconductor substrate using the etch mask.

20. The method according to claim 16, wherein forming the device isolation layer comprises:

forming an etch mask pattern on the semiconductor substrate so as to leave a region of the semiconductor substrate corresponding to the device isolation layer exposed;

etching the exposed region of the semiconductor substrate to form a trench; and

depositing an insulating material layer in the trench.

21. The method according to claim 20, wherein forming the etch mask pattern comprises:

forming a pad oxide film on the semiconductor substrate;

forming a nitride layer on the pad oxide film;

forming a photoresist pattern on the nitride layer so as to mask a region of the nitride layer corresponding to the active region of the semiconductor substrate and leave a portion of the nitride layer exposed; and

etching the nitride layer and the pad oxide layer to form the etch mask pattern comprising a pattern of nitride layer portions stacked on a corresponding pattern of pad oxide film portions.