ALU implementation in single PLD logic cell

• US 6,476,634 B1
• Filed: 02/01/2002
• Issued: 11/05/2002
• Est. Priority Date: 02/01/2002
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Bilski, Goran
• Primary Examiner(s): Chang, Daniel D.
• Application Number:
  US10/061,571
• Time in Patent Office: 277 Days
• Field of Search: 326/37, 326/38, 326/39, 326/40, 326/46, 708/232, 708/235, 708/700
• US Class Current: 326/40
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Structures and methods that implement an ALU (Arithmetic Logic Unit) circuit in a PLD (Programmable Logic Device) while using only one PLD logic cell to implement a one-bit ALU circuit. The ALU circuit has two data input signals and two operator input signals that select between the adder, subtractor, and other logical functions. A result bit provides the result of the addition, subtraction, or other logical function as selected by the values of the two operator input signals. A carry chain is provided for combining the one-bit ALU circuits to generate multi-bit ALUs. All of this functionality is implemented in a single PLD logic cell per ALU bit.

Claims

1. An ALU circuit implemented in a Programmable Logic Device (PLD), the ALU circuit comprising:

first and second data input terminals providing first and second data input signals, respectively;

first and second operator input terminals providing first and second operator input signals, respectively;

a carry-in input terminal;

a carry-out output terminal;

a result output terminal;

a function generator coupled to the first and second data input terminals and the first and second operator input terminals, the function generator being configured to provide;

an XOR function of the first and second data input signals and the first operator input signal, the XOR function providing an XOR output signal;

a first multiplexer function of the first and second data input signals, providing a result of a first logical function to a first multiplexer output signal when the first operator input signal is high and providing a result of a second logical function to the first multiplexer output signal when the first operator input signal is low, the first and second logical functions each being functions of at least one of the first and second data input signals; and

a second multiplexer function of the XOR output signal and the first multiplexer output signal, providing the XOR output signal to a function generator output terminal when the second operator input signal is high and providing the first multiplexer output signal to the function

generator output terminal when the second operator

input signal is low;

an AND gate coupled to the first data input terminal and the second operator input terminal and having an AND output terminal;

a carry multiplexer having a zero data input terminal coupled to the AND output terminal, a one data input terminal coupled to the carry-in terminal, an output terminal coupled to the carry-out terminal, and a select input terminal coupled to the function generator output terminal; and

an XOR circuit having a first input terminal coupled to the function generator output terminal, a second input terminal coupled to the carry-in terminal, and an output terminal coupled to the result output terminal.

2. The ALU circuit of claim 1, wherein the function generator comprises a four-input look-up table.

3. The ALU circuit of claim 1, wherein the PLD is a Field Programmable Gate Array (FPGA).

4. The ALU circuit of claim 3, wherein the function generator is configured using an FPGA bitstream to provide the XOR function and the first and second multiplexer functions.

5. The ALU circuit of claim 1, wherein the first logical function provides the first data input signal and the second logical function provides the second data input signal.

6. The ALU circuit of claim 1, wherein the first and second logical functions are each selected from a group consisting of:

an AND function, an OR function, an XOR function, a NAND function, a NOR function, and an XNOR function.

7. A method for configuring a logic cell in a Programmable Logic Device (PLD) to implement an ALU function, the logic cell comprising a function generator, an AND gate, a carry multiplexer, and an XOR gate, the method comprising:

configuring the function generator to provide a function generator output signal, the function generator output signal being a result of a first logical function when a first operator input signal is high and a second operator input signal is low, being a result of a second logical function when the first and second operator input signals are both low, and being an XOR function of first and second data input signals and the first operator input signal when the second operator input signal is high, the first and second logical functions each being a function of at least one of the first and second data input signals;

configuring the logic cell such that the AND gate provides to the carry multiplexer an output signal comprising an AND function of the first data input signal and the second operator input signal;

configuring the logic cell such that the carry multiplexer provides a carry-out signal to the carry-out terminal of the logic cell, the carry-out signal being the AND gate output signal when the function generator output signal is low and being a carry-in input signal of the logic cell when the function generator output signal is high; and

configuring the logic cell such that the XOR gate provides a result output signal comprising an XOR function of the function generator output signal and the carry-in input signal.

8. The method of claim 7, wherein the PLD comprises the logic cell and a second cell similar to the logic cell, the method further comprising:

configuring the second cell in the same fashion as the configuration of the logic cell;

configuring the PLD such that the first operator input signals of the logic cell and the second cell are the same; and

configuring the PLD such that the second operator input signals of the logic cell and the second cell are the same.

9. The method of claim 8, further comprising:

configuring at least one of the logic cell and the second cell such that the carry-out signal of the logic cell is provided as the carry-in signal of the second cell.

10. The method of claim 7, wherein configuring the function generator comprises configuring a four-input look-up table.

11. The method of claim 7, wherein the PLD is a Field Programmable Gate Array (FPGA).

12. The method of claim 11, wherein the configuring steps are all performed by downloading a single bitstream into the FPGA to provide the described functionality in the logic cell.

13. The method of claim 7, wherein the first logical function provides the first data input signal and the second logical function provides the second data input signal.

14. The method of claim 7, wherein the first and second logical functions are each selected from a group consisting of:

an AND function, an OR function, an XOR function, a NAND function, a NOR function, and an XNOR function.

15. A computer storage device comprising configuration data to configure a logic cell in a Programmable Logic Device (PLD) to implement an ALU function, the logic cell comprising a function generator, an AND gate, a carry multiplexer, and an XOR gate, the configuration data comprising:

a first set of the configuration data that configures the function generator to provide a function generator output signal, the function generator output signal being a result of a first logical function when a first operator input signal is high and a second operator input signal is low, being a result of a second logical function when the first and second operator input signals are both low, and being an XOR function of the first and second data input signals and the first operator input signal when the second operator input signal is high, the first and second logic functions each being a function of at least one of the first and second data input signals;

a second set of the configuration data that configures the logic cell such that the AND gate provides to the carry multiplexer an output signal comprising an AND function of the first data input signal and the second operator input signal;

a third set of the configuration data that configures the logic cell such that the carry multiplexer provides a carry-out signal to a carry-out terminal of the logic cell, the carry-out signal being the AND gate output signal when the function generator output signal is low and being a carry-in input signal of the logic cell when the function generator output signal is high; and

a fourth set of the configuration data that configures the logic cell such that the XOR gate provides a result output signal comprising an XOR function of the function generator output signal and the carry-in input signal.

16. The computer storage device of claim 15, wherein the PLD comprises the logic cell and a second cell similar to the logic cell, the computer storage device further comprising:

a fifth set of the configuration data that configures the second cell in the same fashion as the configuration of the logic cell;

a sixth set of the configuration data that configures the PLD such that the first operator input signals of the logic cell and the second cell are the same; and

a seventh set of the configuration data that configures the PLD such that the second operator input signals of the logic cell and the second cell are the same.

17. The computer storage device of claim 16, further comprising:

an eighth set of the configuration data that configures at least one of the logic cell and the second cell such that the carry-out signal of the logic cell is provided as the carry-in signal of the second cell.

18. The computer storage device of claim 15, wherein the first, second, third, and fourth sets of the configuration data are included in a single computer file.

19. The computer storage device of claim 18, wherein the first, second, third, and fourth sets of the configuration data are interleaved in the single computer file.

20. The computer storage device of claim 15, wherein the first set of the configuration data configures a four-input look-up table to provide the function generator output signal.

21. The computer storage device of claim 15, wherein the PLD is a Field Programmable Gate Array (FPGA).

22. The computer storage device of claim 21, wherein the first, second, third, and fourth sets of the configuration data are included in a single computer file that comprises a configuration bitstream for the FPGA.

23. The computer storage device of claim 22, wherein the first, second, third, and fourth sets of the configuration data are interleaved in the configuration bitstream.

24. The computer storage device of claim 15, wherein the first logical function provides the first data input signal and the second logical function provides the second data input signal.

25. The computer storage device of claim 15, wherein the first and second logical functions are each selected from a group consisting of:

an AND function, an OR function, an XOR function, a NAND function, a NOR function, and an XNOR function.