Tileable field-programmable gate array architecture

• US 6,476,636 B1
• Filed: 09/02/2000
• Issued: 11/05/2002
• Est. Priority Date: 09/02/2000
• Status: Expired due to Fees

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Lien, Jung-Cheun, Feng, Sheng, Huang, Eddy C., Sun, Chung-yuan, Liu, Tong, Liao, Naihui
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/654,240
• Time in Patent Office: 794 Days
• Field of Search: 326/38-41
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3947 global
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

Claims

1. An apparatus including a field programmable gate array (FPGA), the FPGA comprising:

a first FPGA tile comprising;

a plurality of functional groups (FGs) arranged in rows and columns, each of the FGs being configurable to receive regular input signals, perform a logic operation, and generate regular output signals;

a regular routing structure coupled to the FGs and configurable to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs;

a plurality of interface groups (IGs) surrounding the plurality of FGs such that one IG is positioned at each end of each row and column, each of the IGs being coupled to the regular routing structure and configurable to transfer signals from the regular routing structure to outside of the FPGA tile and each of the IGs having a plurality of input multiplexers configurable to select signals received from outside of the FPGA tile and provide signals to the regular routing structure inside the FPGA tile; and

a plurality of input/output pads (I/Os) coupled to at least one of said input multiplexers of at least one of said IGs.

2. The apparatus in accordance with claim 1, wherein each of the IGs further comprises:

a plurality of output multiplexers configured to select signals received from the regular routing structure and provide the selected signals to outside of the FPGA tile.

3. The apparatus in accordance with claim 1, wherein the FPGA further comprises:

a second FPGA tile that includes a plurality of FGs, a regular routing structure, and a plurality of IGs arranged in a manner substantially similar to the first FPGA tile, wherein at least one IG of the first FPGA tile is coupled to at least one IG of the second FPGA tile.

4. The apparatus in accordance with claim 3, wherein the FPGA further comprises:

a third FPGA tile that includes a plurality of FGs, a regular routing structure, and a plurality of IGs arranged in a manner substantially similar to the first FPGA tile, wherein at least one IG of the first FPGA tile is coupled to at least one IG of the third FPGA tile.

5. The apparatus in accordance with claim 1, wherein the apparatus further comprises a system-on-a-chip (SOC).

6. The apparatus in accordance with claim 1, wherein each of the FGs further comprises:

a multiplexer configured to select one of the regular output signals as an FG secondary routing signal.

7. The apparatus in accordance with claim 6, wherein the first FPGA tile further comprises:

a secondary routing structure that is independent of the regular routing structure and that is configured to select and route the FG secondary routing signal around the first FPGA tile.

8. The apparatus in accordance with claim 7, wherein each of the IGs further comprises:

a multiplexer configured to select a signal received from outside of the FPGA tile as an IG secondary routing signal, wherein the secondary routing structure configured to select and route the IG secondary routing signal around the first FPGA tile.

9. The apparatus in accordance with claim 7, wherein the secondary routing structure further comprises:

a secondary routing bus coupled to a secondary routing input of each FG.

10. The apparatus in accordance with claim 9, wherein the secondary routing structure further comprises:

a plurality of first buses with a different first bus corresponding to each row of FGs and that is coupled to receive the FG secondary routing signal from each FG;

a plurality of secondary multiplexers with at least one secondary multiplexer being coupled to each first bus to select a signal therefrom; and

a plurality of buffers with a different buffer being coupled to each secondary multiplexer and having an output coupled to the secondary routing bus.