Low temperature co-fired ceramic substrate structure having a capacitor and thermally conductive via

• US 6,477,054 B1
• Filed: 08/10/2000
• Issued: 11/05/2002
• Est. Priority Date: 08/10/2000
• Status: Active Grant

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Hagerup, William A.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Alcala, Jose H.
• Application Number:
  US09/636,128
• Time in Patent Office: 817 Days
• Field of Search: 174/252, 174/262, 361/760, 361/782, 361/783, 361/793, 361/792, 361/795, 361/794, 361/719, 361/720, 361/713, 361/704, 361/712, 361/714, 361/715, 361/717, 361/709, 257/712, 257/717
• US Class Current: 361/720
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/066 Heatsink mounted on the surface of the PCB heatsink inserted in the PCB H05K2201/10416
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/10969 Metallic case or integral heatsink of component electrically connected to a pad on PCB
• CPC Class Codes: H05K 3/4053 by thick-film techniques

Abstract

A low temperature co-fired ceramic substrate structure has first and second conductive patterns respectively disposed on first and second dielectric layers with the conductive patterns being separated by the first dielectric layer. The first conductive pattern has a first conductive element functioning as a first plate of a capacitor and a second conductive element functioning as a voltage potential lead for an integrated circuit device. The second conductive pattern is positioned below the first conductive pattern and functions as the second plate of the capacitor and as a thermally conductive heat transfer layer for the integrated circuit device. At least a first thermally conductive via is formed between the top and bottom surfaces of the second dielectric layer and below the second conductive element with the via thermally coupled to the second conductive pattern. The thermal via or vias may be thermally coupled to a heat sink disposed adjacent to the bottom surface of the second dielectric layer.

Claims

1. A low temperature co-fired ceramic substrate structure for receiving an integrated circuit device mounted thereon where the bottom surface of the integrated circuit device is a voltage input lead for the integrated circuit device comprising:

first and second dielectric layers having top and bottom surfaces;

a first conductive pattern formed on the top surface of the first dielectric layer having a first conductive element functioning as a first plate of a capacitor and a second conductive element functioning as a voltage potential lead for the integrated circuit;

a second conductive pattern disposed between the first and second dielectric layers and positioned below the first conductive pattern functioning as a second plate of the capacitor and as a thermally conductive heat transfer layer for the integrated circuit device; and

at least a first thermally conductive via formed between the top and bottom surfaces of the second dielectric layer and below the second conductive element and thermally coupled to the second conductive pattern.

2. The substrate structure as recited in claim 1 wherein the thermally conductive via comprises cylindrically formed bores filled with gold.

3. The substrate structure as recited in claim 1 further comprising a heat sink disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the thermally conductive via.

4. The substrate structure as recited in claim 1 further comprising a third conductive pattern formed on the bottom surface of the second dielectric layer that is thermally coupled to the thermally conductive via.

5. The substrate structure as recited in claim 4 further comprising a heat sink disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the third conductive pattern.

6. The substrate structure recited in claim 5 wherein the thermally conductive via is electrically conductive.

7. The substrate structure as recited in claim 1 further comprising a plurality of thermally conductive via formed between the top and bottom surfaces of the second dielectric layer below the second conductive element and thermally coupled to the second conductive element.

8. The substrate structure as recited in claim 7 wherein the plurality of thermally conductive vias comprise cylindrically formed bores filled with gold.

9. The substrate structure as recited in claim 8 wherein the plurality of cylindrically formed thermally conductive vias have a diameter of approximately 0.010 inches.

10. The substrate structure as recited in claim 9 wherein the plurality of thermally conductive vias are formed in a matrix pattern.

11. The substrate structure as recited in claim 10 wherein the plurality of thermally conductive vias in the matrix pattern have a center to center separation of approximately 0.020 inches.

12. The substrate structure as recited in claim 11 further comprising a heat sink disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the plurality of thermally conductive vias.

13. The substrate structure as recited in claim 12 wherein the plurality of thermally conductive vias are electrically conductive.

14. The substrate structure as recited in claim 11 further comprising a third conductive pattern formed on the bottom surface of the second dielectric layer that is thermally coupled to the plurality of thermally conductive vias.

15. The substrate structure as recited in claim 14 further comprising a heat sink disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the third conductive pattern.

16. The substrate structure as recited in claim 15 wherein the plurality of thermally conductive vias are electrically conductive.

17. The substrate structure as recited in claim 1 wherein the first dielectric layer has a thickness of approximately 0.004 inches.

18. The substrate structure as recited in claim 1 wherein the second dielectric layer has a thickness of approximately 0.025 inches.

19. The substrate structure as recited in claim 1 wherein the first and second conductive patterns have a thickness of approximately 0.0005 inches.