Semiconductor device, microcomputer and flash memory

• US 6,477,090 B2
• Filed: 08/28/2001
• Issued: 11/05/2002
• Est. Priority Date: 09/04/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Hiraki, Mitsuru, Tanaka, Toshihiro, Yamaki, Takashi, Fujito, Masamichi, Takeuchi, Kan, Shinagawa, Yutaka
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/939,708
• Publication Number:
  US 20020027233A1
• Time in Patent Office: 434 Days
• Field of Search: 365/226, 365/189.09, 365/185.33, 365/185.01, 365/185.21, 365/185.2, 365/189.07, 365/189.08, 327/540, 327/541, 327/544
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance

Abstract

A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

Claims

1. A semiconductor device on a semiconductor chip, comprising:

a control voltage generating circuit which generates a control voltage on the basis of control data;

a circuit using a current source generating a reference current on the basis of said control voltage;

a current measuring transistor whose control terminal is connected to a signal line for providing said control voltage to said reference current source;

an external measuring terminal, connected to a current terminal of said current measuring transistor, for making possible external measurement of a current flowing in said current measuring transistor; and

a memory means which holds said control data and provides them to said control voltage generating circuit.

2. The semiconductor device according to claim 1, further comprising a plurality of circuits having said current source, wherein said control voltage is commonly provided to said current source of each of said plurality of circuits.

3. The semiconductor device according to claim 2, wherein said current source contains a current source MOS transistor receiving said control voltage at its control terminal and subjected to the control of mutual conductance.

4. The semiconductor device according to claim 3, wherein said current measuring transistor is a MOS transistor manufactured in the same process as said current source MOS transistor.

5. The semiconductor device according to claim 3, wherein said current measuring transistor is of the same size as said current source MOS transistor and is comprised of a plurality of MOS transistors connected to one another in parallel.

6. The semiconductor device according to claim 5, wherein said current measuring transistor is an n-channel type MOS transistor.

7. The semiconductor device according to claim 6, wherein the channel length of said current measuring transistor is set to a channel length whose fluctuations accompany no significant variations in threshold voltage.

8. The semiconductor device according to claim 6, wherein the channel width of said current measuring transistor is set to a channel width whose fluctuations accompany no significant variations in threshold voltage.

9. The semiconductor device according to claim 2, wherein said current source has a current source circuit capable of supplying a reference voltage which includes a current source MOS transistor receiving said control voltage at its control terminal and subjected to the control of mutual conductance and a current mirror load.

10. The semiconductor device according to claim 9, wherein said circuit using said current source is a delay circuit having a delay element, and the delay time of said delay element is controlled with a voltage supplied from said current source circuit.

11. The semiconductor device according to claim 9, wherein said circuit using said current source is a ring oscillator having a plurality of delay elements, and the delay times of said delay elements are controlled with a reference voltage supplied from said current source circuit.

12. The semiconductor device according to claim 9, wherein said circuit using said current source is a ring oscillator having a plurality of delay elements and a timer having a counter for counting periodic signals supplied from said ring oscillator and supplying pulse, and wherein the delay times of said delay elements are controlled with a reference voltage supplied from said current source circuit.

13. The semiconductor device according to claim 9, wherein said circuit using said current source has, as circuits for selectively making a reference current flow, a first MOS transistor and a second MOS transistor receiving at their respective control terminals a reference voltage supplied from said current source circuit and a third MOS transistor arranged between those first and second MOS transistors and subjected to switching control.

14. The semiconductor device according to claim 9, wherein said circuit using said current source has, as circuits for selectively making a charging reference current flow, a first MOS transistor and a second MOS transistor receiving at their respective control terminals a reference voltage supplied from said current source circuit and a third MOS transistor arranged between those first and second MOS transistors and subjected to switching control;

and as a circuit for selectively making a discharging reference current flow, a fourth MOS transistor subjected to switching control complementarily with said third MOS transistor and connected in series to said second MOS transistor.

15. The semiconductor device according to claim 9,

wherein said circuit using said current source has, as first circuits for selectively making a charging reference current flow, a first MOS transistor and a second MOS transistor receiving at their respective control terminals a first voltage supplied from said current source circuit and a third MOS transistor arranged between those first and second MOS transistors and subjected to switching control; and as second circuits for selectively making a discharging reference current flow, a fourth MOS transistor and a fifth MOS transistor receiving at their respective control terminals a second voltage supplied from said current source circuit and a sixth MOS transistor arranged between those fourth and fifth MOS transistors and subjected to switching control.

16. The semiconductor device according to claim 3, wherein said circuit using said current source is a clamp circuit provided with a differential amplifier having said current source MOS transistor as its current source and with an output circuit receiving at its control terminal the differential output voltage of said differential amplifier, said clamp circuit being capable of negatively feeding back the output voltage of said output circuit to the voltage via said differential amplifier.

17. The semiconductor device according to claim 3, comprising:

a non-volatile memory element whose threshold voltage is made programmable;

a reference circuit for generating a decision level for a voltage emerging on a data line according to the threshold voltage of said non-volatile memory element; and

a sense amplifier for comparing the decision level of said reference circuit and the voltage emerging on the data line according to the threshold voltage of said non-volatile memory element,

wherein said reference circuit constitutes a circuit having on its discharge path said current source MOS transistor and using said current source.

18. The semiconductor device according to claim 17, wherein said reference circuit has, as circuits for selectively making a reference current flow, a first MOS transistor and a second MOS transistor receiving at their respective control terminals a voltage and a third MOS transistor arranged between those first and second MOS transistors and subjected to switching control.

19. The semiconductor device according to claim 3, comprising:

a non-volatile memory element whose threshold voltage is made electrically changeable;

a program control circuit for controlling the threshold voltage change for said non-volatile memory element; and

a verify sense amplifier for detecting whether or not the threshold voltage change by said program control circuit has been completed,

wherein said verify sense amplifier includes;

a logic gate having a prescribed logic threshold voltage connected to the data terminal element of said non-volatile memory element;

a current source circuit, having said current source MOS transistor, for generating a reference voltage in the vicinity of said logic threshold voltage on the basis of a current flowing therein; and

a load MOS transistor, receiving said reference voltage generated by said current source circuit and subjected to mutual conductance control, for supplying a current to the data terminal of said non-volatile memory element and, when the threshold voltage of said non-volatile memory element has reached a prescribed state, controlling the input to the logic gate to a voltage in the vicinity of said logic threshold voltage.

20. The semiconductor device according to claim 19, further comprising:

a first selecting circuit provided between said external measuring terminal and said current measuring transistor;

a second selecting circuit; and

another circuit connected between said external measuring terminal and said first selecting circuit via said second selecting circuit.

21. The semiconductor device according to claim 20, wherein said other circuit is a voltage output circuit for supplying a voltage according to voltage control data stored in the memory, and the voltage supplied by said voltage output circuit is made observable from said external measuring terminal via said second selecting circuit.

22. A microcomputer including a CPU and other circuits over one semiconductor chip,

wherein said other circuits include a control voltage generating circuit for generating a control voltage on the basis of control data;

a circuit using a current source transistor for generating a reference current on the basis of said control voltage;

a current measuring transistor whose control terminal is connected to a path for supplying said control voltage to said current source transistor;

an external measuring terminal, connected to the current terminal of said current measuring transistor, for making possible external measurement of the current flowing in said current measuring transistor; and

a memory which holds control data and provides them to said control voltage generating circuit.

23. The microcomputer according to claim 22, wherein said memory includes a non-rewritable non-volatile memory holding control data.

24. The microcomputer according to claim 22, wherein said memory includes an electrically rewritable non-volatile memory.

25. The microcomputer according to claim 24, wherein said memory further includes a register for making control data transferable from said non-volatile memory, making control data transferable from outside, and supplying the transferred control data to the control voltage generating circuit.

26. The microcomputer according to claim 22,

wherein said other circuits include a CPU-accessible flash memory,

wherein said flash memory has an array of non-volatile memory elements whose threshold voltages are made electrically changeable, a program circuit for changing the threshold voltages of said non-volatile memory elements, and a read circuit for reading out stored information in the non-volatile memory elements,

wherein said read circuit has a reference circuit for generating a decision level for a voltage emerging on a data line according to the threshold voltages of said non-volatile memory elements, and a sense amplifier for comparing the decision level of said reference circuit with the voltage emerging on the data line according to the threshold voltages of said non-volatile memory elements, and

wherein said reference circuit is a circuit having on its discharge path said current source MOS transistor and using said current source transistor.

27. The microcomputer according to claim 26, wherein said reference circuit comprises a first current source MOS transistor and a second current source MOS transistor receiving at their respective control terminals a voltage and a third MOS transistor arranged between those first and second MOS transistors and subjected to switching control, and said reference circuit is a circuit making a reference current flow in the turned-on state of said third MOS transistor.

28. The microcomputer according to claim 26, wherein said program circuit has a verify sense amplifier for detecting whether or not the threshold voltage change has been completed,

wherein said verify sense amplifier has:

a logic gate having a prescribed logic threshold voltage connected to the data terminal element of said non-volatile memory element;

a current source circuit, having said current source MOS transistor, for generating a reference voltage in the vicinity of said logic threshold voltage on the basis of a current flowing therein; and

a load MOS transistor, receiving said reference voltage generated by said current source circuit and subjected to mutual conductance control, for supplying a current to the data terminal of said non-volatile memory element and, when the threshold voltage of said non-volatile memory element has reached a prescribed state, controlling the input to the logic gate to a voltage in the vicinity of said logic threshold voltage.

29. The microcomputer according to claim 28, wherein said program circuit sets one of four or more threshold voltages designated by multi-bit programming data for each non-volatile memory element, said read circuit supplies the state of the threshold voltage as corresponding multi-bit stored information, and a multi-value flash memory in which stored information in each non-volatile memory element is expressed in a plurality of bits is thereby realized.

30. The microcomputer according to claim 22, wherein said other circuits include a CPU-accessible RAM,

wherein said RAM has an array of volatile memory elements, a write circuit writing into said volatile memory elements, and a read circuit for reading out stored information in the volatile memory elements,

wherein said read circuit has a reference circuit for generating a decision level for a voltage emerging on a data line according to the stored information of said volatile memory elements, and a sense amplifier for comparing the decision level of said reference circuit with the voltage emerging on the data line according to the stored information of said volatile memory elements, and

wherein said reference circuit is a circuit having on its discharge path said current source MOS transistor and using said current source transistor.

31. A flash memory having over one semiconductor chip an array of non-volatile memory elements whose threshold voltages are made electrically changeable, a program circuit for changing the threshold voltages of said non-volatile memory elements, and a read circuit for reading out stored information in the non-volatile memory elements,

either said program circuit or read circuit or both have a current source MOS transistor, receiving a control voltage, for generating a reference current,

said flash memory further including:

a signal line for providing a control voltage to said current source MOS transistor;

a current measuring MOS transistor whose control terminal is connected to said signal line;

an external measuring terminal, connected to the current terminal of said current measuring MOS transistor, for making possible external measurement of the current flowing in said current measuring MOS transistor;

a control voltage generating circuit for generating said control voltage on the basis of control data; and

a memory for holding said control data and providing them to said control voltage generating circuit.

32. The flash memory according to claim 31,

wherein said read circuit has a reference circuit for generating a decision level for a voltage emerging on a data line according to the threshold voltages of said non-volatile memory elements, and a sense amplifier for comparing the decision level of said reference circuit with the voltage emerging on the data line according to the threshold voltages of said non-volatile memory elements, and

wherein said reference circuit is a circuit having on its discharge path said current source MOS transistor and using said current source transistor.

33. The flash memory according to claim 32, wherein said reference circuit comprises a first current source MOS transistor and a second current source MOS transistor receiving at their respective control terminals a voltage and a third MOS transistor arranged between said first and second current source MOS transistors and subjected to switching control, and wherein the reference circuit is a circuit making a current flow in the turned-on state of said third MOS transistor.

34. The flash memory according to claim 31,

wherein said program circuit has a verify sense amplifier for detecting whether or not the threshold voltage change has been completed,

wherein said verify sense amplifier includes:

a logic gate having a prescribed logic threshold voltage connected to the data terminal element of said non-volatile memory element;

a current source circuit, having said current source MOS transistor, for generating a reference voltage in the vicinity of said logic threshold voltage on the basis of a current flowing therein; and

a load MOS transistor, receiving said reference voltage generated by said current source circuit and subjected to mutual conductance control, for supplying a current to the data terminal of said non-volatile memory element and, when the threshold voltage of said non-volatile memory element has reached a prescribed state, controlling the input to the logic gate to a voltage in the vicinity of said logic threshold voltage.

35. The flash memory according to claim 34, wherein said program circuit sets one of four or more threshold voltages designated by multi-bit programming data for each non-volatile memory element, said read circuit supplies the state of the threshold voltage as corresponding multi-bit stored information for each non-volatile memory element, and a multi-value flash memory in which stored information in each non-volatile memory element is expressed in a plurality of bits is thereby realized.