Multiple device access to serial data stream

• US 6,477,177 B1
• Filed: 06/22/1998
• Issued: 11/05/2002
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Potts, David Lawson
• Primary Examiner(s): LUTHER, WILLIAM A
• Application Number:
  US09/100,891
• Time in Patent Office: 1,597 Days
• Field of Search: 370/431, 370/437, 710/105, 710/36, 710/37, 710/38, 710/40, 710/43, 710/45, 710/217, 710/203, 710/100
• US Class Current: 370/437
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0278 Band edge detection

Abstract

One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor'"'"'s respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g., by a write to a write direction extra bits register addressable through a specific input/output (I/O) location. The extra bits are tacked on to a subsequent write cycle in the digital serial interface, e.g., in the AC '"'"'97 link, to write an excess length data word. In the read direction, each read cycle places excess bits in a read direction extra bits register for reading in a subsequent read cycle. Another aspect of the invention provides an automatic status register which provides, e.g., automatic creation of a TAG Phase in time slot 0 of an AC '"'"'97 link using, e.g., a write enable signal to various resources in the digital serial interface, e.g., write enable signals to time slot registers.

Claims

1. A device for allowing a plurality of processors access to a common digital serial interface, comprising:

a first write direction data bus corresponding to access to said digital serial interface from a first processor;

a second write direction data bus corresponding to access to said digital serial interface from a second processor;

a first data register in communication with said first write direction data bus;

a second data register in communication with said second write direction data bus;

a multiplexer to select one of said first data register and said second data register for output to said digital serial interface; and

a configuration register to control said multiplexer.

2. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

said configuration register is adapted and arranged to be set by only one of said first processor and said second processor.

3. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

said configuration register is adapted and arranged to be set by any one of said first processor and said second processor.

4. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, further comprising:

a plurality of read direction data buses.

5. The device for allowing a plurality of processors access to a common digital serial interface according to claim 4, wherein said plurality of read direction data buses comprise:

a first read direction data bus corresponding to said first processor; and

a second read direction data bus corresponding to said second processor.

6. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

at least one of said first processor and said second processor is a digital signal processor.

7. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

said first processor and said second processor are each a digital signal processor.

8. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, further comprising:

an output FIFO device receiving an output from said multiplexer device.

9. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

said digital serial interface comprises a plurality of time slots.

10. The device for allowing a plurality of processors access to a common digital serial interface according to claim 9, wherein:

said plurality of time slots is at least twelve time slots .

11. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

said configuration register is adapted and arranged to control said multiplexer on a time slot basis.

12. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

respective bits in said configuration register correspond to the output during time slot periods of a selection of one of said first write direction data bus and said second write direction data bus.

13. The device for allowing a plurality of processors access to a common digital serial interface according to claim 1, wherein:

said device is included in an audio codec.

14. The device for allowing a plurality of processors access to a common digital serial interface according to claim 13, wherein:

said audio codec is substantially in conformance with the “

AC '"'"'97 Audio Codec '"'"'97 Component Specification”

, revision 1.03, Sep. 15, 1996.

15. A method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface, comprising:

providing a first write direction data bus for accessing said common digital serial interface from a first processor;

providing a second write direction data bus for accessing said common digital serial interface from a second processor; and

multiplexing between said first write direction data bus and said second write direction data bus on a time slot-wise basis for output to said common digital serial interface.

16. The method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 15, further comprising:

buffering said time slot-wise multiplexed data in a FIFO device.

17. The method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 15, further comprising:

outputting said time slot-wise multiplexed data in a single serial data stream to said common digital serial interface.

18. The method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 15, further comprising:

correlating bits in a configuration register to respective time slots in said time slot-wise multiplexed data.

19. The method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 15, further comprising:

providing a first configuration register for indicating time slots of said common digital serial interface which are assigned to said first processor.

20. The method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 19, further comprising:

providing a second configuration register for indicating time slots of said common digital serial interface which are assigned to said second processor.

21. Apparatus for providing a plurality of processors access to a plurality of time slots of a common digital serial interface, comprising:

means for providing a first write direction data bus for accessing said common digital serial interface from a first processor;

means for providing a second write direction data bus for accessing said common digital serial interface from a second processor; and

means for multiplexing between said first write direction data bus and said second write direction data bus on a time slot-wise basis for output to said common digital serial interface.

22. The apparatus for providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 21, further comprising:

means for buffering said time slot-wise multiplexed data in a FIFO device.

23. The apparatus for providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 21, further comprising:

means for outputting said time slot-wise multiplexed data in a single serial data stream to said common digital serial interface.

24. The apparatus for providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 21, further comprising:

means for correlating bits in a configuration register to respective time slots in said time slot-wise multiplexed data.

25. The method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface according to claim 21, further comprising:

means for providing a first configuration register for indicating time slots of said common digital serial interface which are assigned to said first processor.

26. A system, comprising:

an analog codec interface;

a plurality of devices coupled to said analog codec interface and sharing access thereto; and

a configuration register coupled to each of said plurality of devices;

wherein a device requesting write access to said analog codec interface is adapted to issue a request signal and poll said configuration register to obtain information corresponding to a data slot for which write access is granted.