Multi-pair gigabit ethernet transceiver

• US 6,477,200 B1
• Filed: 11/09/1999
• Issued: 11/05/2002
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kruse, David E., Hatamian, Mehdi, Creigh, John L., Agazzi, Oscar E., Samueli, Henry, Abnous, Arthur
• Primary Examiner(s): Corrielus, Jean
• Application Number:
  US09/437,719
• Time in Patent Office: 1,092 Days
• Field of Search: 375/229, 375/233, 375/254, 375/260, 375/259, 375/285, 375/346, 375/348, 375/350, 375/262, 375/265, 375/224, 375/227, 375/286
• US Class Current: 375/233
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/235 combined with adaptive equaliser
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0021 in which the algorithm uses adaptive thresholds
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 : not time-recursive
• CPC Class Codes: H04L 2025/0349 : as a feedback filter
• CPC Class Codes: H04L 2025/03496 : as a prediction filter
• CPC Class Codes: H04L 2025/03503 : as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 : Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 : Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03197 : methods of calculation involving metrics
• CPC Class Codes: H04L 25/03203 : Trellis search techniques
• CPC Class Codes: H04L 25/03235 : with state-reduction using feedback filtering
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/03987 : Equalisation for sparse channels
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Claims

1. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

measurement circuitry configured to measure a performance degradation characteristic resulting from disabling one or more portions of at least one circuit element

disabling circuitry configured to adaptively disable said one or more portions of the at least one circuit element until the performance degradation characteristic reaches a threshold level; and

a decision feedback sequence estimation (DFSE) circuit operatively coupled with the at least one circuit element, the DFSE decoding an input sample into a final decision corresponding to a codeword of a trellis code having N states, the DFSE comprising;

a decoder circuit that is operative to decode a set of signal samples to generate tentative decisions and the final decision; and

a single state decision feedback equalizer.

2. The integrated circuit communication device according to claim 1, the decision feedback equalizer coupled to the decoder circuit for receiving the tentative decisions, the single state decision feedback equalizer comprising:

a set of low-ordered coefficients; and

a set of high-ordered coefficients generating a tail value based on the tentative decisions and the input sample.

3. The integrated circuit communication device according to claim 2, further comprising a state multiplication circuit, the state multiplication circuit expanding a single state representation of a signal received from the single state decision feedback equalizer into an N state representation suitable for decoding by the DFSE.

4. The integrated circuit communication device according to claim 3, the state multiplication circuit comprising a multiple decision feedback equalizer coupled to the decision-feedback equalizer and generating an N state representation of signal samples in response to the tail value and the set of low-ordered coefficients received from the decision feedback equalizer.

5. The integrated circuit communication device according to claim 1, the DFSE circuit further comprising:

a Viterbi decoder that is adapted to receive the set of signal samples, the Viterbi decoder computing path metrics for each of the N states of the trellis code and outputting decisions based on the path metrics; and

a path memory module coupled to the Viterbi decoder to receive the decisions, the path memory module having a number of depth levels corresponding to consecutive time instants, each of the depth levels including N registers for storing decisions corresponding to the N states, each of selected depth levels including a multiplexer for selecting a best decision from corresponding N registers, the best decision at the last depth level being the final decision, the best decisions at other selected depth levels being the tentative decisions.

6. The integrated circuit communication device according to claim 4, the multiple decision feedback equalizer comprising;

a memory;

a set of symbolic levels contained within the memory; and

a convolution engine coupled to combine the set of low order coefficients with each symbolic level of the set of symbolic levels.

7. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

measurement circuitry configured to measure a performance degradation characteristic resulting from disabling one or more portions of at least one circuit element;

disabling circuitry configured to adaptively disable said one or more portions of the at least one circuit element until the performance degradation characteristic reaches a threshold level; and

a single state decision feedback equalizer operatively coupled with the at least one circuit element.

8. The integrated circuit communication device according to claim 7, the single state decision feedback equalizer having a set of ordered coefficients, the decision feedback equalizer defining a coefficient related tail value and a low order subset of coefficient values.

9. The integrated circuit communication device according to claim 8, wherein the single state decision feedback equalizer has a width dimension D, wherein the width dimension D corresponds to the number of pairs defining the multi-pair transmission channel.

10. The integrated circuit communication device according to claim 9, further comprising a state multiplication circuit, the state multiplication circuit expanding a single state representation output signal received from the single state decision feedback equalizer into an N state representation signal.

11. The integrated circuit communication device according to claim 10, the state multiplication circuit comprising:

a convolution engine coupled to combine the low order subset of coefficient values with each member of a set of symbolic levels to define a first sample signal set; and

a summing circuit coupled to combine the tail value with each sample signal of the first sample signal set to define an N state representational set of signal samples.

12. The integrated circuit communication device according to claim 7, further comprising:

a control module controlling activation and deactivation of at least a portion of the sub-pluralities of the circuit elements according to a criterion, the criterion being based on at least one of an information error metric, a power metric, a specified error and a specified power; and

a computing module coupled to the control module, the computing module computing at least one of the information error metric and the power metric.

13. The integrated circuit communication device according to claim 12, wherein the criterion is the following:

activate if the information error metric is greater than the specified error; and

deactivate if the information error metric is smaller than the specified error.

14. The integrated circuit communication device according to claim 13, wherein the criterion is the following:

activate if the information error metric is greater than the specified error and the power metric is smaller than the specified power; and

deactivate if the information error metric is smaller than the specified error or the power metric is greater than the specified power.

15. The integrated circuit communication device according to claim 14, wherein the information error metric is related to a bit error rate of the communication system.

16. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

a first intersymbol interference (ISI) compensation circuit receiving an input signal and outputting a second signal, the second signal being substantially compensated for a first ISI component, the first ISI compensation circuit comprising an equalizer circuit comprising;

an ISI compensation filter having a substantially inverse impulse response to the impulse response of a pulse shaping filter of a remote transmitter; and

an adaptive gain stage; and

a second ISI compensation circuit, the second ISI compensation circuit receiving the second signal and generating a third signal, the third signal being substantially compensated for a second ISI component.

17. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

a first intersymbol interference (ISI) compensation circuit receiving an input signal and outputting a second signal, the second signal being substantially compensated for a first ISI component; and

a second ISI compensation circuit, the second ISI compensation circuit receiving the second signal and generating a third signal, the third signal being substantially compensated for a second ISI component, the second ISI compensation circuit comprising a decision feedback sequence estimation circuit comprising;

a decoder circuit receiving and decoding at least one ISI compensated signal sample, and generating tentative decisions and a final decision; and

a decision feedback equalizer coupled in feedback fashion to the decoder circuit, the decision feedback equalizer including a set of low-ordered coefficients and a set of high-ordered coefficients, the decision feedback equalizer generating a first portion of ISI compensation for the second ISI component based on the tentative decisions and the high-ordered coefficients.

18. The integrated circuit communication device according to claim 17, wherein the decision feedback sequence estimation circuit further comprises a convolution engine coupled to the decision feedback equalizer to receive values of the low-ordered coefficients, the convolution engine computing a set of pre-computed values representing a set of potential second ISI compensation portions for the second ISI component.

19. The integrated circuit communication device according to claim 18, wherein a first digital signal is combined with the first portion of ISI compensation to produce a second digital signal partially compensated for the second ISI component.

20. The integrated circuit communication device according to claim 19, wherein the decision feedback sequence estimation circuit further comprises a multiple decision feedback equalizer coupled to the decision feedback equalizer and the convolution engine, the multiple decision feedback equalizer combining the set of pre-computed values with the second digital signal to produce a set of potential digital signals, one of the potential digital signals being substantially compensated for the second ISI component.

21. The integrated circuit communication device according to claim 20, wherein the first ISI component represents ISI introduced by a remote transmission device, and wherein the second ISI component represents ISI introduced by transmission channel characteristics.

22. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

measurement circuitry configured to measure a performance degradation characteristic resulting from disabling one or more portions of at least one circuit element;

disabling circuitry configured to adaptively disable said one or more portions of the at least one circuit element until the performance degradation characteristic reaches a threshold level;

a first intersymbol interference (ISI) compensation circuit operatively coupled with the at least one circuit element and configured to compensate for a transmitter induced ISI component; and

a second ISI compensation circuit operatively coupled with the first ISI compensation circuit and configured to compensate for a transmission channel induced ISI component.

23. The integrated circuit communication device according to claim 22, the first ISI compensation device comprising an equalizer circuit, including:

an ISI compensation filter having a substantially inverse impulse response to the impulse response of a pulse shaping filter of a remote transmitter; and

an adaptive gain stage.

24. The integrated circuit communication device according to claim 22, the second ISI compensation device comprising a decision feedback sequence estimation circuit.

25. The integrated circuit communication device according to claim 24, the decision feedback sequence estimation circuit comprising:

a decoder circuit receiving and decoding at least one ISI compensated signal sample, and generating tentative decisions and a final decision; and

a decision feedback equalizer coupled in feedback fashion to the decoder circuit, the decision feedback equalizer including a set of low-ordered coefficients and a set of high-ordered coefficients, the decision feedback equalizer generating a first portion of ISI compensation for the second ISI component based on the tentative decisions and the high-ordered coefficients.

26. The integrated circuit communication device according to claim 25, wherein the decision feedback sequence estimation circuit further comprises a convolution engine coupled to the decision feedback equalizer to receive values of the low-ordered coefficients, the convolution engine computing a set of pre-computed values representing a set of potential second ISI compensation portions for the second ISI component.

27. The integrated circuit communication device according to claim 26, wherein a first digital signal is combined with the first portion of ISI compensation to produce a second digital signal partially compensated for the second ISI component.

28. The integrated circuit communication device according to claim 27, wherein the decision feedback sequence estimation circuit further comprises a multiple decision feedback equalizer coupled to the decision feedback equalizer and the convolution engine, the multiple decision feedback equalizer combining the pre-computed values with the second digital signal to produce a set of potential digital signals, one of the potential digital signals being substantially compensated for the second ISI component.

29. The integrated circuit communication device according to claim 28, wherein the first ISI component represents ISI introduced by a remote transmission device, and wherein the second ISI component represents ISI introduced by transmission channel characteristics.

30. The integrated circuit communication device according to claim 22, further comprising:

a control module controlling activation and deactivation of one or more portions of the at least one circuit element according to a criterion, the criterion being based on at least one of an information error metric, a power metric, a specified error and a specified power; and

a computing module coupled to the control module, the computing module computing at least one of the information error metric and the power metric.

31. The integrated circuit communication device according to claim 30, wherein the criterion is the following:

activate if the information error metric is greater than the specified error; and

deactivate if the information error metric is smaller than the specified error.

32. The integrated circuit communication device according to claim 31, wherein the criterion is the following:

activate if the information error metric is greater than the specified error and the power metric is smaller than the specified power; and

deactivate if the information error metric is smaller than the specified error or the power metric is greater than the specified power.

33. The integrated circuit communication device according to claim 32, wherein the information error metric is related to a bit error rate of the communication system.

34. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

measurement circuitry configured to measure a performance degradation characteristic resulting from disabling one or more portions of at least one circuit element;

disabling circuitry configured to adaptively disable said one or more portions of the at least one circuit element until the performance degradation characteristic reaches a threshold level; and

a decoder system operatively coupled with the at least one circuit element, for computing the distance of a received symbolic word from a codeword.

35. The integrated circuit communication device according to claim 34, further comprising:

a control module controlling activation and deactivation of one or more portions of the at least one circuit element according to a criterion, the criterion being based on at least one of an information error metric, a power metric, a specified error and a specified power; and

a computing module coupled to the control module, the computing module computing at least one of the information error metric and the power metric.

36. The integrated circuit communication device according to claim 35, wherein the criterion is the following:

activate if the information error metric is greater than the specified error; and

deactivate if the information error metric is smaller than the specified error.

37. The integrated circuit communication device according to claim 36, wherein the criterion is the following:

activate if the information error metric is greater than the specified error and the power metric is smaller than the specified power; and

deactivate if the information error metric is smaller than the specified error or the power metric is greater than the specified power.

38. The integrated circuit communication device according to claim 37, wherein the information error metric is related to a bit error rate of the communication system.

39. The integrated circuit communication device according to claim 34, configured to receive information encoded in accordance with a multi-level symbolic scheme and over a multi-dimensional transmission channel, the decoder system comprising:

an input, coupled to receive an input signal;

a first slicer, coupled to detect the input signal with respect to a first one of two disjoint one-dimensional symbol-subsets; and

a second slicer, coupled to detect the input signal with respect to a second one of the two disjoint one-dimensional symbol-subsets;

wherein the first slicer outputs a first decision term and a first error term with respect to the first one of the two disjoint one-dimensional symbol-subsets, the second slicer outputting a second decision term and a second error term with respect to the second one of the two disjoint one-dimensional symbol-subsets; and

wherein each of the first and second error terms is expressed by a digital representation having substantially fewer bits than the input signal.

40. The integrated circuit communication device according to claim 39, wherein each of the first and second error terms represents a distance metric between the input signal and a symbol in the respective one of the two disjoint one-dimensional symbol-subsets.

41. The integrated circuit communication device according to claim 34, configured to receive information encoded in accordance with a multi-level symbolic scheme and over a multi-dimensional transmission channel, the decoder system comprising:

an input to receive an input signal;

a first slicer coupled to the input, the first slicer detecting the input signal with respect to a first one of two disjoint one-dimensional symbol-subsets;

a second slicer coupled to the input, the second slicer detecting the input signal with respect to a second one of the two disjoint one-dimensional symbol-subsets; and

a third slicer coupled to detect the input signal with respect to a union set of the two disjoint one-dimensional symbol-subsets.

42. The integrated circuit communication device according to claim 41, wherein the first slicer outputs a first decision with respect to the first one of the two disjoint one-dimensional symbol-subsets, the second slicer outputting a second decision with respect to the second one of the two disjoint one-dimensional symbol-subsets, and wherein the third slicer outputs a third decision with respect to the union set of the two disjoint one-dimensional symbol-subsets.

43. The integrated circuit communication device according to claim 42, further comprising:

a first combination logic block configured to combine the first decision with the third decision, the first combination logic block defining a second error term; and

a second combination logic block configured to combine the second decision with the third decision, the second combination logic block defining a second error term.

44. The integrated circuit communication device according to claim 43, further comprising:

a first square error generation block configured to operate on the first error term so as to define a square error representation thereof; and

a second square error generation block configured to operate on the second error term so as to define a square error representation thereof.

45. The integrated circuit communication device according to claim 44, wherein each of the error terms is expressed as a digital representation having one bit.

46. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

a first intersymbol interference (ISI) compensation circuit configured to compensate for a transmitter induced ISI component;

a second ISI compensation circuit operatively coupled with the first ISI compensation circuit and configured to compensate for a transmission channel induced ISI component;

a decoder system operatively coupled with the second ISI compensation circuit, for computing the distance of a received symbolic word from a codeword; and

wherein the first ISI compensation circuit comprises;

an inverse partial response filter having an impulse response substantially an inverse of an impulse response of a pulse shaping filter of a remote transmitter, so as to substantially compensate an input digital signal for a first ISI component.

47. The integrated circuit communication device according to claim 46, wherein the inverse partial response filter is implemented with a characteristic feedback gain factor K.

48. The integrated circuit communication device according to claim 47, wherein the inverse partial response filter operates in accordance with a non-zero value of the characteristic feedback gain factor K during communication initialization and wherein the value of the feedback gain factor K is ramped down to zero after a pre-defined interval.

49. The integrated circuit communication device according to claim 48, wherein the second ISI compensation circuit comprises:

a Viterbi decoder configured to decode a digital signal and generate tentative decisions; and

feedback equalizer circuitry coupled to the Viterbi decoder, the feedback equalizer circuitry receiving the tentative decisions and combining the tentative decisions with a set of high-ordered coefficients to generate a first value.

50. The integrated circuit communication device according to claim 49, wherein the second ISI compensation circuit further comprises:

summing circuitry combining the first value with a digital signal, the summing circuitry outputting an intermediate signal; and

a multiple decision feedback equalizer receiving the intermediate signal and combining the intermediate signal with a set of pre-computed values generated by combining values of a set of low-ordered coefficients with a set of values representing levels of a multi-level symbolic alphabet to produce a set of potential digital signals, one of the potential digital signals being substantially ISI compensated, the multiple decision feedback equalizer outputting said one of the potential digital signals to the Viterbi decoder.

51. The integrated circuit communication device according to claim 50, wherein the characteristic feedback gain factor K is ramped to zero after convergence of the decision feedback equalizer.

52. The integrated circuit communication device according to claim 46, the codeword being a concatenation of L symbols selected from two disjoint symbol-subsets X and Y, the codeword being included in one of a plurality of code-subsets, the received word being represented by L inputs, each of the L inputs uniquely corresponding to one of L dimensions, the decoder system comprising:

a set of slicers for producing a set of one-dimensional errors from the L inputs, each of the one-dimensional errors representing a distance metric between one of the L-inputs and a symbol in one of the two disjoint symbol-subsets; and

a combining module for combining the one-dimensional errors to produce a set of L-dimensional errors such that each of the L-dimensional errors is a distance of the received word from a nearest codeword in one of the code-subsets.

53. The integrated circuit communication device according to claim 52, wherein each of the one-dimensional errors is represented by substantially fewer bits than each of the L inputs.

54. The integrated circuit communication device according to claim 52, wherein the slicers slice the L inputs with respect to each of the two disjoint symbol-subsets X and Y to produce a set of X-based errors, a set of Y-based errors and corresponding sets of X-based and Y-based decisions, the sets of X-based and Y-based errors forming the set of one-dimensional errors, the sets of X-based and Y-based decisions forming the set of one-dimensional decisions, each of the X-based and Y-based decisions being a symbol in a corresponding symbol-subset closest in distance to one of the L inputs, each of the one-dimensional errors representing a distance metric between a corresponding one-dimensional decision and one of the L inputs.

55. The integrated circuit communication device according to claim 52, wherein the set of slicers comprises:

first slicers for slicing each of the L inputs with respect to each of the two disjoint symbol-subsets X and Y to produce a set of X-based decisions and a set of Y-based decisions, the sets of X-based and Y-based decisions forming the set of one-dimensional decisions, each of the X-based and Y-based decisions being a symbol in a corresponding symbol-subset closest in distance to one of the L inputs;

second slicers for slicing each of the L inputs with respect to a symbol-set comprising all symbols of the two disjoint symbol-subsets to produce a set of hard decisions; and

error-computing modules for combining each of the sets of X-based and Y-based decisions with the set of hard decisions to produce the set of one-dimensional errors, each of the one-dimensional errors representing a distance metric between the corresponding one-dimensional decision and one of the L inputs.

56. The integrated circuit communication device according to claim 52, wherein the combining module comprises:

a first set of adders for combining one-dimensional errors to produce two-dimensional errors;

a second set of adders for combining the two-dimensional errors to produce intermediate L-dimensional errors, the intermediate L-dimensional errors being arranged into pairs of errors such that the pairs of errors correspond one-to-one to the code-subsets; and

a minimum-select module for determining a minimum for each of the pairs of errors, each minimum being one of the L-dimensional errors.

57. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

a decision feedback sequence estimation (DFSE) circuit, for decoding an input sample into a final decision corresponding to a codeword of a trellis code having N states, the DFSE comprising a single state decision feedback equalizer; and

a decoder system for computing the distance of a received symbolic word from a codeword;

wherein the single state decision feedback equalizer comprises a set of ordered coefficients, the decision feedback equalizer further defining a coefficient related tail value and a low order subset of coefficient values.

58. The integrated circuit communication device according to claim 57, wherein the single state decision feedback equalizer has a width dimension D, wherein the width dimension D corresponds to the number of pairs defining the multi-pair transmission channel.

59. The integrated circuit communication device according to claim 58, further comprising a state multiplication circuit, the state multiplication circuit expanding a single state representation output signal received from the single state decision feedback equalizer into an N state representation signal suitable for decoding by the DFSE.

60. The integrated circuit communication device according to claim 57, configured to receive information encoded in accordance with a multi-level symbolic scheme and over a multi-dimensional transmission channel, the decoder system comprising:

an input, coupled to receive an input signal;

a first slicer, coupled to detect the input signal with respect to a first one of two disjoint one-dimensional symbol-subsets; and

a second slicer, coupled to detect the input signal with respect to a second one of the two disjoint one-dimensional symbol-subsets;

wherein the first slicer outputs a first decision term and a first error term with respect to the first one of the two disjoint one-dimensional symbol-subsets, the second slicer outputting a second decision term and a second error term with respect to the second one of the two disjoint one-dimensional symbol-subsets; and

wherein each of the first and second error terms is expressed by a digital representation having substantially fewer bits than the input signal.

61. The integrated circuit communication device according to claim 60, wherein each of the first and second error terms represents a distance metric between the input signal and a symbol in the respective one of the two disjoint one-dimensional symbol-subsets.

62. The integrated circuit communication device according to claim 59, configured to receive information encoded in accordance with a multi-level symbolic scheme and over a multi-dimensional transmission channel, the decoder system comprising:

an input to receive an input signal;

a first slicer coupled to the input, the first slicer detecting the input signal with respect to a first one of two disjoint one-dimensional symbol-subsets;

a second slicer coupled to the input, the second slicer detecting the input signal with respect to a second one of the two disjoint one-dimensional symbol-subsets; and

a third slicer coupled to detect the input signal with respect to a union set of the two disjoint one-dimensional symbol-subsets.

63. The integrated circuit communication device according to claim 62, wherein the first slicer outputs a first decision with respect to the first one of the two disjoint one-dimensional symbol-subsets, the second slicer outputting a second decision with respect to the second one of the two disjoint one-dimensional symbol-subsets, and wherein the third slicer outputs a third decision with respect to the union set of the two disjoint one-dimensional symbol-subsets.

64. The integrated circuit communication device according to claim 63, further comprising:

a first combination logic block configured to combine the first decision with the third decision, the first combination logic block defining a first error term; and

a second combination logic block configured to combine the second decision with the third decision, the second combination logic block defining a second error term.

65. The integrated circuit communication device according to claim 64, further comprising:

a first square error generation block configured to operate on the first error term so as to define a square error representation thereof; and

a second square error generation block configured to operate on the second error term so as to define a square error representation thereof.

66. The integrated circuit communication device according to claim 63, wherein each of the error terms is expressed as a digital representation having one bit.

67. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

a decision feedback sequence estimation (DFSE) circuit that is operative to decode an input sample into a final decision corresponding to a codeword of a trellis code having N states, the DFSE including a single state decision feedback equalizer;

a first ISI compensation circuit configured to compensate for a transmitter induced ISI component;

a second ISI compensation circuit configured to compensate for a transmission channel induced ISI component; and

adaptive circuitry that is operative to reduce power consumption of a filter, the filter having an initial set of active coefficients, an input and an output, the active coefficients being ordered, a lowest ordered active coefficient of the initial set being proximal to the input, each of the active coefficients having a stable value.

68. The integrated circuit communication device according to claim 67, further comprising:

a threshold module generating a threshold;

a comparing module coupled to the threshold module, the comparing module comparing an active coefficient with the threshold; and

a decision module coupled to the comparing module, the decision module deactivating the active coefficient according to criterion.

69. The integrated circuit communication device according to claim 68, wherein the decision module deactivates the active coefficient if the active coefficient has a value smaller than the threshold.

70. The integrated circuit communication device according to claim 69, further comprising:

a buffer providing a specified error;

an error computing module computing a error metric; and

a second comparing module coupled to the buffer, the error computing module and the threshold module, the second comparing module comparing the error metric with the specified error and producing a first control signal to the threshold module when the error metric is smaller than the specified error and a second control signal to the threshold module when the error metric is larger than the specified error.

71. The integrated circuit communication device according to claim 70, wherein the threshold module updates the threshold upon reception of the first or second control signal.

72. The integrated circuit communication device according to claim 67, wherein the first ISI compensation circuit comprises:

an inverse partial response filter having an impulse response substantially an inverse of an impulse response of a pulse shaping filter of a remote transmitter, so as to substantially compensate an input digital signal for a first ISI component.

73. The integrated circuit communication device according to claim 72, wherein the inverse partial response filter is implemented with a characteristic feedback gain factor K.

74. The integrated circuit communication device according to claim 73, wherein the inverse partial response filter operates in accordance with a non-zero value of the characteristic feedback gain factor K during communication initialization and wherein the value of the feedback gain factor K is ramped down to zero after a pre-defined interval.

75. The integrated circuit communication device according to claim 74, wherein the second ISI compensation circuit comprises:

a Viterbi decoder configured to decode a digital signal and generate tentative decisions; and

feedback equalizer circuitry coupled to the Viterbi decoder, the feedback equalizer circuitry receiving the tentative decisions and combining the tentative decisions with a set of high-ordered coefficients to generate a first value.

76. The integrated circuit communication device according to claim 75, wherein the second ISI compensation circuit further comprises:

summing circuitry combining the first value with a digital signal, the summing circuitry outputting an intermediate signal; and

a multiple decision feedback equalizer receiving the intermediate signal and combining the intermediate signal with a set of pre-computed values generated by combining values of a set of low-ordered coefficients with a set of values representing levels of a multi-level symbolic alphabet to produce a set of potential digital signals, one of the potential digital signals being substantially ISI compensated, the multiple decision feedback equalizer outputting said one of the potential digital signals to the Viterbi decoder.

77. The integrated circuit communication device according to claim 76, wherein the characteristic feedback gain factor K is ramped to zero after convergence of the decision feedback equalizer.

78. The integrated circuit communication device according to claim 67, the single state decision feedback equalizer having a set of ordered coefficients, the decision feedback equalizer defining a coefficient related tail value and a low order subset of coefficient values.

79. The integrated circuit communication device according to claim 78, wherein the single state decision feedback equalizer has a width dimension D, wherein the width dimension D corresponds to the number of pairs defining the multi-pair transmission channel.

80. The integrated circuit communication device according to claim 79, further comprising a state multiplication circuit, the state multiplication circuit expanding a single state representation output signal received from the single state decision feedback equalizer into an N state representation signal suitable for decoding by the DFSE.

81. The integrated circuit communication device according to claim 80, the state multiplication circuit comprising:

a convolution engine coupled to combine the low order subset of coefficient values with each member of a set of symbolic levels to define a first sample signal set; and

a summing circuit coupled to combine the tail value with each member of the first sample signal set to define an N state representational set of signal samples.

82. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

measurement circuitry configured to measure a performance degradation characteristic resulting from disabling one or more portions of at least one circuit element;

disabling circuitry configured to adaptively disable said one or more portions of the at least one circuit element until the performance degradation characteristic reaches a threshold level;

a first intersymbol interference (ISI) compensation circuit operatively coupled with the at least one circuit element and configured to compensate for a transmitter induced ISI component;

a second ISI compensation circuit operatively coupled with the first ISI compensation circuit and configured to compensate for a transmission channel induced ISI component; and

a decoder system that is operatively coupled with the second ISI compensation circuit and operative to compute the distance of a received symbolic word from a codeword.