Method for implementing multiple memory buses on a memory module

• US 6,477,614 B1
• Filed: 09/08/2000
• Issued: 11/05/2002
• Est. Priority Date: 09/30/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Horine, Bryce D., Leddige, Michael W., Bonella, Randy, MacWilliams, Peter D.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/658,293
• Time in Patent Office: 788 Days
• Field of Search: 711/5, 711/115, 711/170, 710/131, 714/56
• US Class Current: 711/5
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.

Claims

1. A method for routing signals to a memory module having a memory repeater hub, comprising:

determining, by a first memory repeater hub of the first memory module, whether the signals received address a memory device on a first memory module;

routing the signals to a first memory bus on the first memory module connected to the memory device, if the addressed memory device is on the first memory module; and

routing the signals to a second memory repeater hub of the second memory module that is connected to the first memory module, if the addressed memory device is not on the first memory module;

determining, by the second memory repeater hub, whether the signals received address a memory device on the second memory module; and

routing the signals to a second memory bus on the second memory module connected to the memory device, if the addressed memory device is on the second memory module.

2. The method of claim 1, further comprising routing the signals to a third memory repeater hub of the third memory module connected to the second memory module, if the addressed memory device is not on the second memory module.

3. The method of claim 1, wherein the first memory module further comprises a fourth memory bus connected in series with the first memory bus via the first memory repeater hub, and wherein the first and the third memory buses are coupled in parallel with respect to each other.

4. The method of claim 3, further comprising:

determining whether the addressed memory device is on the first or the fourth memory bus;

routing the signals to the first memory bus if the addressed memory device is on the first memory bus; and

routing the signals to the fourth memory bus if the addressed memory device is on the fourth memory bus.

5. The method of claim 1, further comprising de-serializing command and address information from the signals, wherein the determination is performed based on the address information.

6. The method of claim 1, further comprising reformatting data into a format appropriate for a memory device of the memory module.

7. A method for routing signals on a memory module, comprising:

determining, by a memory repeater hub coupled to the memory module, whether signals received address a memory device on the memory module;

routing the signals to a first memory bus on the memory module connected to the memory device if the addressed memory device is on the memory module; and

routing the signals to a second memory bus that is connected to the memory module if the addressed memory device is not on the memory module.

8. The method of claim 7, wherein the determining whether a memory device to which signals are addressed is on the first memory module, comprises:

reading a first portion of address information to identify the identity of the memory device;

reading a second portion of the address information to identify the identity of a memory bus that the memory device is connected to; and

comparing the identity of the memory device and the identity of the memory bus to first memory module information.

9. The method of claim 7, wherein a de-multiplexed protocol is utilized in the memory repeater hub.

10. A method for routing signals to memory modules, comprising:

de-serializing command and address information from the signals;

determining whether the signals received address a memory device on a first memory module, based on the address information;

routing the signals to a first memory bus on the first memory module coupled to the memory device, if the addressed memory device is on the first memory module; and

routing the signals to a second memory bus that is connected to the first memory module, if the addressed memory device is not on the first memory module.

11. The method of claim 10, wherein determining whether the signals received address a memory device on the first memory module, comprises:

reading a first portion of the address information to identify the identity of the memory device;

reading a second portion of the address information to identify the identity of a memory bus that the memory device is connected to; and

comparing the identity of the memory device and the identity of the memory bus to memory module information.

12. The method of claim 10, wherein the determination is performed by a memory repeater hub.

13. The method of claim 12, wherein a de-multiplexed protocol is utilized in the memory repeater hub.

14. The method of claim 10, wherein the first memory module and the second memory module are connected through an electrical connector.

15. The method of claim 10, further comprising reformatting data into a format appropriate for memory devices of memory modules.

16. A machine-readable medium having stored thereon executable code which causes a machine to perform a method, for routing signals on a memory module, the method comprising:

determining, by a memory repeater hub coupled to the memory module, whether signals received address a memory device on the memory module;

routing the signals to a first memory bus on the memory module connected to the memory device if the addressed memory device is on the memory module; and

routing the signals to a second memory bus that is connected to the memory module, if the addressed memory device is not on the memory module.

17. The machine-readable medium of claim 16, wherein determining whether the signals received address a memory device on the first memory module, comprises:

reading a first portion of the address information to identify the identity of the memory device;

reading a second portion of the address information to identify the identity of a memory bus that the memory device is connected to; and

comparing the identity of the memory device and the identity of the memory bus to memory module information.

18. A machine-readable medium having stored thereon executable code which causes a machine to perform a method, for routing signals to memory modules, the method comprising:

de-serializing command and address information from the signals;

determining whether the signals received address a memory device on a first memory module, based on the address information;

routing the signals to a first memory bus on the first memory module coupled to the memory device, if the addressed memory device is on the first memory module; and

routing the signals to a second memory bus located on a second memory module that is connected to the first memory module, if the addressed memory device is not located on the first memory module.

19. The machine-readable medium of claim 18, wherein determining whether the signals received address a memory device on the first memory module, comprises:

reading a first portion of the address information to identify the identity of the memory device;

reading a second portion of the address information to identify the identity of a memory bus that the memory device is connected to; and

comparing the identity of the memory device and the identity of the memory bus to memory module information.

20. A machine-readable medium having stored thereon executable code which causes a machine to perform a method, for routing signals to memory having a memory repeater hub, the method comprising:

determining, by a first memory repeater hub of the first memory module, whether the signals received address a memory device on a first memory module;

routing the signals to a first memory bus on the first memory module connected to the memory device, if the addressed memory device is on the first memory module; and

routing the signals to a second memory repeater hub of the second memory module that is connected to the first memory module, if the addressed memory device is not on the first memory module;

determining, by the second memory repeater hub, whether the signals received address a memory device on the second memory module; and

routing the signals to a second memory bus on the second memory module connected to the memory device, if the addressed memory device is on the second memory module.

21. The machine-readable medium of claim 20, wherein the first memory module further comprises a fourth memory bus connected in series with the first memory bus via the first memory repeater hub, and wherein the first and the third memory buses are coupled in parallel with respect to each other.

22. The machine-readable medium of claim 21, wherein the method further comprises:

determining whether the addressed memory device is on the first or the fourth memory bus;

routing the signals to the first memory bus if the addressed memory device is on the first memory bus; and

routing the signals to the fourth memory bus if the addressed memory device is on the fourth memory bus.