Parallel access virtual channel memory system

• US 6,477,621 B1
• Filed: 11/10/1999
• Issued: 11/05/2002
• Est. Priority Date: 11/18/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Incorporated (NEC Corporation)
• Inventors: Lee, Jeffery H., Ando, Manabu
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US09/438,001
• Time in Patent Office: 1,091 Days
• Field of Search: 711/118, 711/119, 711/120, 711/147, 711/150, 710/38, 710/31
• US Class Current: 711/120
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches

Abstract

A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Claims

1. A method of accessing, with a plurality of memory masters, a memory array having a plurality of memory banks, the method comprising the steps of:

coupling a virtual access system to the memory array, wherein the virtual access system comprises a plurality of virtual access channels connected in parallel to the memory array, each virtual access channel providing a set of memory access resources for accessing any of the plurality of memory banks of the memory array;

assigning each of the memory masters to access one or more of the virtual access channels;

providing address signals from the memory masters to the virtual access system; and

accessing a selected one of the virtual access channels in response to the address signals.

2. The method of claim 1, further comprising the steps of:

storing a cache entry and a corresponding cache address entry in the selected one of the virtual access channels;

comparing the address signals with the cache address entry; and

accessing the cache entry corresponding if the current access address matches the cache address entry.

3. The method of claim 2, further comprising the steps of accessing the memory array through a bus bypass circuit and updating the selected one of the virtual access channels to reflect this accessing if the address signals do not match the cache address entry.

4. The method of claim 1, further comprising the step of simultaneously activating two of the virtual access channels.

5. The method of claim 1, further-comprising the step of chaining a plurality of the virtual access channels.

6. The method of claim 1, further comprising the step of independently assigning a burst length to each of the virtual access channels.

7. The method of claim 1, further comprising the step of independently assigning a precharge mode to each of the virtual access channels.

8. The method of claim 1, further comprising the step of prefetching data from the memory array to a selected one of the virtual access channels in response to a prefetch command issued by one of the memory masters.

9. The method of claim 8, further comprising the step of transferring data between one of the memory masters and one of the virtual access channels concurrently with the step of prefetching data.

10. The method of claim 8, further comprising the step of restoring data from a selected one of the virtual access channels to the memory array in response to a restore command issued by one of the memory masters, wherein the step of restoring data is performed concurrently with the step of prefetching data.

11. The method of claim 1, wherein the memory array comprises a plurality of memory banks, the method further comprising the step of concurrently prefetching data from a plurality of the multiple banks to a corresponding plurality of the virtual access channels in response to a plurality of prefetch commands issued by the memory masters.

12. The method of claim 1, further comprising the step of restoring data from a selected one of the virtual access channels to the memory array in response to a restore command issued by one of the memory masters.

13. The method of claim 12, further comprising the step of transferring data between one of the memory masters and one of the virtual access channels concurrently with the step of restoring data.

14. The method of claim 1, further comprising the step of concurrently restoring data from a plurality of the virtual access channels to a corresponding plurality of the memory banks in response to a plurality of restore commands issued by the memory masters.