Methods and arrangements for automatic synthesis of systems-on-chip

• US 6,477,691 B1
• Filed: 04/03/2000
• Issued: 11/05/2002
• Est. Priority Date: 04/03/2000
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bhattacharya, Subhrajit, Daveau, Jean-Marc R., Bergamashi/Rab, Reinaldo A., Lee, William R.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US09/542,025
• Time in Patent Office: 946 Days
• Field of Search: 716/12, 716/1, 716/8-11, 716/13-14
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Processes and arrangements for describing a system-on-chip at an abstract level. Contemplated is the creation of a “virtual design” and its automatic synthesis into a “real design that includes IP blocks from a library as well as all required interconnections and interface logic between them. Significant reductions in the complexity, time and cost associated with system-on-chip designs can be enjoyed as a result.

Claims

1. A method of predetermining interconnections between at least two cores in a system-on-chip, said method comprising the steps of:

establishing a virtual design for said system-on-chip, the virtual design including at least two virtual components, at least one virtual pin associated with each virtual component, and at least one virtual interconnection between at least one pair of virtual pins; and

automatically transforming the virtual design into a real design, the real design including at least two real components, at least one real pin associated with each real component and at least one real interconnection between at least one pair of real pins;

wherein said transforming step comprises determining the at least one real interconnection based on the compatibility between different real pins.

2. The method according to claim 1, further comprising, prior to said step of determining the at least one real interconnection:

determining at least one corresponding real component for each virtual component; and

determining at least one corresponding real pin for each virtual pin; and

determining the compatibility between at least two real pins whose corresponding virtual pins share at least one common virtual interconnection.

3. The method according to claim 2, wherein said step of determining at least one corresponding real component comprises at least one of the following (A) and (B):

(A) determining at least one corresponding real component by default; and

(B) determining at least one corresponding real component via accessing a virtual component library that specifies at least one available real component corresponding to at least one virtual component.

4. The method according to claim 1, wherein said step of determining the at least one real interconnection based on the compatibility between different real pins comprises comparing properties associated with each of said real pins.

5. The method according to claim 1, wherein said transforming step comprises specifying said real pins based on the compatibility between at least one virtual pin in a virtual component and at least one real pin in a corresponding real component.

6. The method according to claim 1, wherein said transforming step comprises:

automatically determining the direction of at least one real pin belonging to a real component; and

automatically determining the required interconnection logic for interconnecting at least two real pins.

7. A system for predetermining interconnections between at least two cores in a system-on-chip, said system comprising:

a virtual design system which establishes a virtual design for said system-on-chip, the virtual design including at least two virtual components, at least one virtual pin associated with each virtual component, and at least one virtual interconnection between at least one pair of virtual pins; and

a transforming system which automatically transforms the virtual design into a real design, the real design including at least two real components, at least one real pin associated with each real component and at least one real interconnection between at least one pair of real pins;

wherein said transforming system is adapted to determine the at least one real interconnection based on the compatibility between different real pins.

8. The system according to claim 7, wherein said transforming system is further adapted to perform the following steps prior to determining the at least one real interconnection:

determining at least one corresponding real component for each virtual component; and

determining at least one corresponding real pin for each virtual pin; and

determining the compatibility between at least two real pins whose corresponding virtual pins share at least one common virtual interconnection.

9. The system according to claim 8, wherein said transforming system is further adapted to determine at least one corresponding real component via at least one of the following steps (A) and (B):

(A) determining at least one corresponding real component by default; and

(B) determining at least one corresponding real component via accessing a virtual component library that specifies at least one available real component corresponding to at least one virtual component.

10. The system according to claim 7, wherein said transforming system is adapted to determine the at least one real interconnection by assessing the compatibility between different real pins via comparing properties associated with each of said real pins.

11. The system according to claim 7, wherein said transforming system is further adapted to specify said real pins based on the compatibility between at least one virtual pin in a virtual component and at least one real pin in a corresponding real component.

12. The system according to claim 7, wherein said transforming system is further adapted to perform the following steps prior to creating a real interconnection between at least two real pins:

automatically determine the direction of at least one real pin belonging to a real component; and

automatically determine the required interconnection logic for interconnecting at least two real pins.

13. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for predetermining interconnections between at least two cores in a system-on-chip, said method comprising:

establishing a virtual design for said system-on-chip, the virtual design including at least two virtual components, at least one virtual pin associated with each virtual component, and at least one virtual interconnection between at least one pair of virtual pins; and

automatically transforming the virtual design into a real design, the real design including at least two real components, at least one real pin associated with each real component and at least one real interconnection between at least one pair of real pins;

wherein said transforming step comprises determining the at least one real interconnection based on the compatibility between different real pins.