Semiconductor device manufacturing method

• US 6,479,305 B2
• Filed: 09/15/1999
• Issued: 11/12/2002
• Est. Priority Date: 09/18/1998
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ohta, Hiroyuki, Tanaka, Shinji, Kono, Ryuji, Miura, Hideo, Endo, Yoshishige, Kanamaru, Masatoshi, Ariga, Akihiko, Ban, Naoto, Aoki, Hideyuki, Hosogane, Atsushi
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Luk, Olivia T
• Application Number:
  US09/396,732
• Publication Number:
  US 20020064893A1
• Time in Patent Office: 1,154 Days
• Field of Search: 438/14, 438/16, 371/22.1, 437/8
• US Class Current: 438/14
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

Claims

1. A semiconductor device manufacturing method comprising the steps of:

forming a plurality of large-scale integrated circuits (LSI) over a semiconductor wafer;

cutting the semiconductor wafer into individual LSI chips, each chip having a main surface and a rear surface opposite from the main surface, the main surface having circuits formed thereon;

rearranging and integrating a predetermined number N of cut LSI chips from among the cut LSI chips in a jig having openings with a size commensurate with the dimensions of the LSI chip, the cut LSI chips being integrated in the jig such that the rear surface of each chip is in contact with the jig and the main surface is exposed for inspection, wherein at least one part of the jig having the openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips;

inspecting the cut LSI chips as a unit through a plurality of inspecting steps, and

screening to select LSI chips basis on an inspection result obtained in said inspecting step.

2. A semiconductor device manufacturing method according to claim 1, wherein said rearranging and integrating step is performed immediately after said cutting step.

3. A semiconductor device manufacturing method according to claim 1, wherein said number N of LSI chips are not fewer than two and are fewer than the total number of LSI chips cut out from the semiconductor wafer.

4. A semiconductor device manufacturing method according to claim 1, wherein said inspecting step includes a burn-in step.

10. A semiconductor device inspection method according to claim 1, wherein the jig is formed by the combination of a base and tray, the tray being formed to have said openings.

5. A semiconductor device inspection method of inspecting semiconductor device chips obtained by forming a plurality of large-scale integrated circuits over the semiconductor wafer and cutting the semiconductor wafer into individual LSI chips, each chip having a main surface and a rear surface opposite from the main surface, the main surface having circuits formed thereon, the method comprising the steps of:

rearranging said cut LSI chips and integrating a predetermined number N of said cut LSI chips in a jig having openings with a size commensurate with the dimensions of the LSI chip, the cut LSI chips being integrated in the jig such that the rear surface of each chip is in contact with the jig and the main surface is exposed for inspection, at least one part of the jig having the openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips;

inspecting said number N of cut LSI chips as a unit through a plurality of inspecting steps; and

screening to select LSI chips basis on an inspection result obtained in said inspecting step.

6. A semiconductor device inspection method according to claim 5, wherein said number N of LSI chips are not fewer than two and are fewer than the total number of LSI chips cut out from the semiconductor wafer.

7. A semiconductor device inspection method according to claim 5, wherein the inspecting step includes a burn-in step.

11. A semiconductor device inspection method according to claim 5, wherein the jig is formed by the combination of a base and tray, the tray being formed to have said openings.

8. A semiconductor device manufacturing method comprising the steps of:

forming a plurality of large-scale integrated circuits (LSI) over a semiconductor wafer;

cutting the semiconductor wafer into individual LSI chips, each chip having a main surface and a rear surface opposite from the main surface, the main surface having circuits formed thereon;

rearranging and integrating a predetermined number N of cut LSI chips from among the cut LSI chips, the cut LSI chips being integrated in the jig such that the rear surface of each chip is in contact with the jig and the main surface is exposed for inspection;

inspecting the cut LSI chips in a jig as a unit through a plurality of inspecting steps; and

screening to select LSI chips based on an inspection result obtained in said inspecting steps.

12. A semiconductor device inspection method according to claim 8, wherein the jig is formed by the combination of a base and tray, the tray being formed to have said openings.

9. A semiconductor device manufacturing method comprising the steps of:

forming a plurality of large-scale integrated circuits (LSI) over a semiconductor wafer;

cutting the semiconductor wafer into individual LSI chips, each chip having a main surface and a rear surface opposite from the main surface, the main surface having circuits formed thereon;

rearranging and integrating a predetermined number N of cut LSI chips from among the cut LSI chips, the cut LSI chips are integrated in a jig, the cut LSI chips being integrated in the jig such that the rear surface of each chip is in contact with the jig and the main surface is exposed for inspection, wherein at least one part of the jig uses silicon;

inspecting the cut LSI chips in a jig as a unit through a plurality of inspecting steps; and

screening to select LSI chips based on an inspection result obtained in said inspecting steps.

13. A semiconductor device inspection method according to claim 9, wherein the jig is formed by the combination of a base and tray, the tray being formed to have said openings.