Method of fabricating high voltage power MOSFET having low on-resistance

• US 6,479,352 B2
• Filed: 01/19/2001
• Issued: 11/12/2002
• Est. Priority Date: 06/02/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/766,229
• Publication Number:
  US 20020009832A1
• Time in Patent Office: 662 Days
• Field of Search: 438/268, 438/14, 438/17, 438/270, 438/138, 438/563, 438/564, 148/DIG.126
• US Class Current: 438/268
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. A plurality of trenches are located in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches. The test structures allow the simultaneous optimization of the breakdown voltage and on-resistance of the device.

Claims

1. A method of forming a high voltage MOSFET comprising the steps of:

providing a substrate of a first conductivity type;

depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively; and

forming a plurality of trenches in said drift region of the epitaxial layer;

filling said trenches with a material having a dopant of the second conductivity type, said trenches extending toward the substrate from the first and second body regions;

diffusing at least a portion of said dopant from said trenches into portions of the epitaxial layer adjacent the trenches;

measuring a breakdown voltage in said epitaxial layer;

comparing the measured breakdown voltage to a predetermined relationship between breakdown voltage and diffusion time to determine a remaining diffusion time to achieve a prescribed breakdown voltage; and

performing an additional diffusion step for said remaining diffusion time.

2. The method of claim 1 wherein said material filling the trench is single crystal silicon or polysilicon.

3. The method of claim 1 wherein said material filling the trench is a dielectric.

4. The method of claim 3 wherein said dielectric is silicon dioxide.

5. The method of claim 1 wherein said dopant is boron.

6. The method of claim 2 further comprising the step of at least partially oxidizing said single crystal silicon or polysilicon.

7. The method of claim 2 further comprising the step of recrystallizing said polysilicon to form single crystal silicon.

8. The method of claim 1 wherein said material filling the trench includes single crystal silicon and a dielectric or polysilicon and a dielectric.

9. The method of claim 1 wherein said body regions include deep body regions.

10. The method of claim 1, wherein said trench is formed by providing a masking layer defining at least one trench, and etching the trench defined by the masking layer.

11. The method of claim 1, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

12. The method of claim 6 further comprising the step of recrystallizing said polysilicon to form single crystal silicon.

13. The method of claim 1 wherein said prescribed breakdown voltage is a maximum breakdown voltage.