Method of manufacturing interconnection structural body

• US 6,479,374 B1
• Filed: 09/27/2000
• Issued: 11/12/2002
• Est. Priority Date: 04/01/1998
• Status: Expired due to Fees

• Current Assignee: Asahi Kasei Kabushiki Kaisha
• Original Assignee: Asahi Kasei Kabushiki Kaisha
• Inventors: Doi, Ichiro, Ioka, Takaaki, Tanabe, Tsuneaki
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/647,310
• Time in Patent Office: 776 Days
• Field of Search: 438/601, 438/624, 438/637, 438/594, 438/737, 438/146, 438/638, 438/303, 438/421, 438/476, 438/786
• US Class Current: 438/601
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02345 treatment by exposure to radiation, e.g. visible light
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass

Abstract

Disclosed is a method for producing a circuit structure having an insulator layer comprising a porous silicon oxide thin film, which comprises (1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on a substrate, which silicon oxide-organic polymer composite thin film comprises a silicon oxide having an organic polymer dispersed therein, (2) forming, in the preliminary insulator layer, a groove which defines a pattern for a circuit, (3) forming, in the groove, a metal layer which functions as a circuit, and (4) removing the organic polymer from the preliminary insulator layer to render the preliminary insulator layer porous, thereby converting the preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film. By the method of the present invention, the capacitance between mutually adjacent circuit lines (line-to-line capacitance) in the circuit structure can be lowered.

Claims

1. A method for producing a circuit structure comprising:

(a) a substrate,

(b) an insulator layer formed on said substrate, said insulator layer comprising a porous silicon oxide thin film having a groove, said groove defining a pattern for a circuit, and

(c) a circuit comprising a metal layer formed in said groove,

said method comprising the steps of;

(1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on said substrate, said silicon oxide-organic polymer composite thin film comprising a silicon oxide having an organic polymer dispersed therein,

(2) forming, in said preliminary insulator layer, a groove which defines a pattern for a circuit,

(3) forming, in said groove, a metal layer which functions as a circuit, and

(4) removing said organic polymer from said silicon oxide-organic polymer composite thin film of said preliminary insulator layer to render said preliminary insulator layer porous, thereby converting said preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film.

2. The method according to claim 1, wherein the removal of said organic polymer from said preliminary insulator layer is conducted by light irradiation-heat treatment.

3. The method according to claim 2, wherein said organic polymer in said silicon oxide-organic polymer composite thin film comprises at least one polymer selected from the group consisting of a polymer having a graft structure and a polymer having a three-dimensional network structure.

4. The method according to claim 1, wherein said organic polymer in said silicon oxide-organic polymer composite thin film comprises at least one polymer selected from the group consisting of a polymer having a graft structure and a polymer having a three-dimensional network structure.

5. A circuit structure produced by the method of claim 1.

6. A multilayer circuit board comprising a laminate of a plurality of circuit structures, wherein at least one circuit structure of said circuit structures is the circuit structure of claim 3.

7. A semiconductor device comprising the circuit structure of claim 4.