III-V compounds semiconductor device with an AlxByInzGa1-x-y-zN non continuous quantum dot layer

• US 6,479,839 B2
• Filed: 05/18/2001
• Issued: 11/12/2002
• Est. Priority Date: 11/18/1997
• Status: Expired due to Term

• Current Assignee: Kyma Technologies, Inc.
• Original Assignee: Technology & Devices International, Inc.
• Inventors: Vassilevski, Konstantin V., Melnik, Yuri V., Dmitriev, Vladimir A., Nikolaev, Audrey E.
• Primary Examiner(s): Chaudhrui, Olik
• Assistant Examiner(s): Louie, Wai-Sing
• Application Number:
  US09/861,180
• Publication Number:
  US 20020030192A1
• Time in Patent Office: 543 Days
• Field of Search: 257/79-103
• US Class Current: 257/82
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0259 Microstructure
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 31/0304 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials

Abstract

A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of Al_xB_yIn_zGa_{1−x−y−z}N, InGaN_1−a−bP_aAs_b, or Al_xB_yIn_zGa_{1−x−y−z}N_1−a−bP_aAs_b.

Claims

1. A compound semiconductor device, comprising:

a substrate;

a first high temperature n-type III-V compound layer having a first band gap grown directly on said substrate, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 900°

C. using HVPE techniques, wherein a low temperature buffer layer is not interposed between said substrate and said high temperature n-type III-V compound layer;

a second n-type III-V compound layer having a second band gap grown on said first high temperature n-type III-V compound layer using HVPE techniques, wherein said first band gap is wider than said second band gap;

a first p-type III-V compound layer having a third band gap grown on said second n-type III-V compound layer using HVPE techniques;

a second p-type III-V compound layer having a fourth band gap grown on said first p-type III-V compound layer using HVPE techniques, wherein said fourth band gap is wider than said third band gap; and

a non-continuous quantum dot layer comprised of a plurality of Al_xB_yIn_zGa<sub>1−

x−

y−

z</sub>N quantum dot regions, said non-continuous quantum dot layer formed between said second n-type III-V compound layer and said first p-type III-V compound layer, wherein 0.01≦

x+y≦

0.2.

2. The compound semiconductor device of claim 1, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 950°

C. using HVPE techniques.

3. The compound semiconductor device of claim 1, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 1000°

C. using HVPE techniques.

4. The compound semiconductor device of claim 1, wherein 0.01≦

x+y≦

0.03 and x+y+z≦

0.2.

5. The compound semiconductor device of claim 1, wherein 0.01≦

x+y≦

0.03 and x+y+z≦

0.15.

6. The compound semiconductor device of claim 1, wherein a majority of said plurality of Al_xB_yIn_zGa₁₋

x−

y−

zN quantum dot regions are less than 30 Angstroms in width, length, and thickness.

7. The compound semiconductor device of claim 1, wherein a majority of said plurality of Al_xB_yIn_zGa₁₋

x−

y−

zN quantum dot regions are approximately 20 Angstroms by 20 Angstroms by 20 Angstroms.

8. The compound semiconductor device of claim 1, further comprising:

a first contact deposited on said second p-type III-V compound layer; and

a second contact deposited on said substrate.

9. The compound semiconductor device of claim 8, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

10. The compound semiconductor device of claim 1, further comprising a third p-type III-V compound layer having a fifth band gap grown on said second p-type III-V compound layer using HVPE techniques, wherein said fourth band gap is wider than said fifth band gap.

11. The compound semiconductor device of claim 10, further comprising:

a first contact deposited on said third p-type III-V compound layer; and

a second contact deposited on said substrate.

12. The compound semiconductor device of claim 11, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

13. The compound semiconductor device of claim 1, wherein said substrate is selected from the group of materials consisting of sapphire, silicon carbide, gallium nitride, and silicon.

14. The compound semiconductor device of claim 1, wherein said first and second p-type III-V compound layers include at least one acceptor impurity metal selected from the group of metals consisting of Mg, Zn, and MgZn.

15. The compound semiconductor device of claim 14, wherein a concentration of said at least one acceptor impurity metal within said first and second p-type III-V compound layers is in the range of 10¹⁸ to 10²¹ atoms cm⁻

3.

16. The compound semiconductor device of claim 14, wherein a concentration of said at least one acceptor impurity metal within said first and second p-type III-V compound layers is in the range of 10¹⁹ to 10²⁰ atoms cm⁻

3.

17. The compound semiconductor device of claim 14, wherein said first and second p-type III-V compound layers are co-doped with O.

18. The compound semiconductor device of claim 10, wherein said third p-type III-V compound layer includes at least one acceptor impurity metal selected from the group of metals consisting of Mg, Zn, and MgZn.

19. The compound semiconductor device of claim 18, wherein a concentration of said at least one acceptor impurity metal within said third p-type III-V compound layer is in the range of 10¹⁸ to 10²¹ atoms cm⁻

3.

20. The compound semiconductor device of claim 18, wherein a concentration of said at least one acceptor impurity metal within said third p-type III-V compound layer is in the range of 10¹⁹ to 10²⁰ atoms cm⁻

3.

21. The compound semiconductor device of claim 18, wherein said third p-type III-V compound layer is co-doped with O.

22. The compound semiconductor device of claim 1, wherein said second n-type III-V compound layer includes at least one donor impurity selected from the group of materials consisting of O, Si, Ge, and Sn.

23. The compound semiconductor device of claim 1, wherein said first high temperature n-type III-V compound layer is comprised of AlGaN.

24. The compound semiconductor device of claim 1, wherein said second n-type III-V compound layer is comprised of GaN or InGaN.

25. The compound semiconductor device of claim 1, wherein said first p-type III-V compound layer is comprised of GaN or InGaN.

26. The compound semiconductor device of claim 1, wherein said second p-type III-V compound layer is comprised of AlGaN.

27. The compound semiconductor device of claim 10, wherein said third p-type III-V compound layer is comprised of GaN.

28. A compound semiconductor device, comprising:

a p-type substrate;

a first high temperature p-type III-V compound layer having a first band gap grown directly on said substrate, wherein said high temperature p-type III-V compound layer is grown at a temperature greater than 800°

C. using HVPE techniques, wherein a low temperature buffer layer is not interposed between said substrate and said high temperature p-type III-V compound layer;

a second p-type III-V compound layer having a second band gap grown on said first high temperature p-type III-V compound layer using HVPE techniques, wherein said first band gap is wider than said second band gap;

a first n-type III-V compound layer having a third band gap grown on said second high temperature p-type III-V compound layer using HVPE techniques;

a second n-type III-V compound layer having a fourth band gap grown on said first n-type III-V compound layer using HVPE techniques, wherein said fourth band gap is wider than said third band gap; and

a non-continuous quantum dot layer comprised of a plurality of Al_xB_yIn_zGa<sub>1−

x−

x−

z</sub>N quantum dot regions, said non-continuous quantum dot layer formed between said second high temperature p-type III-V compound layer and said first n-type III-V compound layer, wherein 0.01≦

x+y≦

0.2.

29. The compound semiconductor device of claim 28, wherein said high temperature p-type III-V compound layer is grown at a temperature greater than 900°

C. using HVPE techniques.

30. The compound semiconductor device of claim 28, wherein said high temperature p-type III-V compound layer is grown at a temperature greater than 950°

C. using HVPE techniques.

31. The compound semiconductor device of claim 28, wherein said high temperature p-type III-V compound layer is grown at a temperature greater than 1000°

C. using HVPE techniques.

32. The compound semiconductor device of claim 28, wherein 0.01≦

x+y≦

0.03 and x+y+z≦

0.2.

33. The compound semiconductor device of claim 28, wherein 0.01≦

x+y≦

0.03 and x+y+z≦

0.15.

34. The compound semiconductor device of claim 28, wherein a majority of said plurality of Al_xB_yIn_zGa₁₋

x−

y−

zN quantum dot regions are less than 30 Angstroms in width, length, and thickness.

35. The compound semiconductor device of claim 28, wherein a majority of said plurality of Al_xB_yIn_zGa₁₋

x−

y−

zN quantum dot regions are approximately 20 Angstroms by 20 Angstroms by 20 Angstroms.

36. The compound semiconductor device of claim 28, further comprising:

a first contact deposited on said second n-type III-V compound layer; and

a second contact deposited on said substrate.

37. The compound semiconductor device of claim 36, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

38. The compound semiconductor device of claim 28, further comprising a third n-type III-V compound layer having a fifth band gap grown on said second n-type III-V compound layer using HVPE techniques, wherein said fourth band gap is wider than said fifth band gap.

39. The compound semiconductor device of claim 38, further comprising:

a first contact deposited on said third n-type III-V compound layer; and

a second contact deposited on said substrate.

40. The compound semiconductor device of claim 39, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

41. The compound semiconductor device of claim 28, wherein said p-type substrate is selected from the group of materials consisting of sapphire, silicon carbide, gallium nitride, and silicon.

42. The compound semiconductor device of claim 28, wherein said first high temperature p-type III-V compound layer and said second p-type III-V compound layer each include at least one acceptor impurity metal selected from the group of metals consisting of Mg, Zn, and MgZn.

43. The compound semiconductor device of claim 42, wherein a concentration of said at least one acceptor impurity metal within said first high temperature p-type III-V compound layer and said second p-type III-V compound layer is in the range of 10¹⁸ to 10²¹ atoms cm⁻

3.

44. The compound semiconductor device of claim 42, wherein a concentration of said at least one acceptor impurity metal within said first high temperature p-type III-V compound layer and said second p-type III-V compound layer is in the range of 10¹⁹ to 10²⁰ atoms cm⁻

3.

45. The compound semiconductor device of claim 42, wherein said first high temperature p-type III-V compound layer and said second p-type III-V compound layer are co-doped with O.

46. The compound semiconductor device of claim 28, wherein said first n-type III-V compound layer includes at least one donor impurity selected from the group of materials consisting of O, Si, Ge, and Sn.

47. The compound semiconductor device of claim 28, wherein said first high temperature p-type III-V compound layer is comprised of AlGaN.

48. The compound semiconductor device of claim 28, wherein said second p-type III-V compound layer is comprised of GaN or InGaN.

49. The compound semiconductor device of claim 28, wherein said first n-type III-V compound layer is comprised of GaN or InGaN.

50. The compound semiconductor device of claim 28, wherein said second n-type III-V compound layer is comprised of AlGaN.

51. The compound semiconductor device of claim 38, wherein said third n-type III-V compound layer is comprised of GaN.