Floating gate isolation device

• US 6,479,880 B1
• Filed: 08/15/2000
• Issued: 11/12/2002
• Est. Priority Date: 07/14/1994
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: González, Fernando
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Berezny, Neal
• Application Number:
  US09/639,623
• Time in Patent Office: 819 Days
• Field of Search: 257/314, 257/68, 257/71, 257/508, 257/409, 257/354, 257/501, 257/510, 257/524, 257/566, 257/523, 438/430, 438/454, 438/429, 438/424-5, 438/400, 438/259, 148/DIG.85
• US Class Current: 257/508
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory device. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.

Claims

1. An isolation structure for semiconductor devices that include a substrate having element forming regions on which semiconductor elements are formed and an isolation structure surrounding each element forming region to provide a plurality of element forming regions electrically isolated from each other, the isolation structure comprising a trench in the substrate, the trench filled with electrically charged polysilicon completely surrounded by insulating material.

2. An isolation structure for semiconductor devices having a substrate, a plurality of word lines arranged parallel to each other and extending in a row direction above the substrate and a plurality of bitlines arranged parallel to each other and extending in a column direction generally perpendicular to and above the word lines, the isolation structure comprising a trench in the substrate, the trench filled with electrically charged polysilicon completely surrounded by insulating material.