MOS current sense circuit

• US 6,479,975 B1
• Filed: 10/16/2001
• Issued: 11/12/2002
• Est. Priority Date: 09/26/2001
• Status: Expired due to Term

• Current Assignee: Dialog Semiconductor plc (Renesas Electronics Corporation)
• Original Assignee: Dialog Semicon
• Inventors: Knoedgen, Horst, Plankensteiner, Manfred
• Primary Examiner(s): Vu, Bao Q.
• Application Number:
  US09/978,232
• Time in Patent Office: 392 Days
• Field of Search: 323/316, 323/312, 323/313, 323/317
• US Class Current: 323/316
• CPC Class Codes: G01R 19/16519 using FET's
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A new current sense circuit has been achieved. The current sense circuit comprises, first, a first MOS transistor having a gate, a drain, and a source. The gate is coupled to a control signal. The drain is coupled to a load such that a load current flows through the first MOS transistor when the control signal is ON. A second MOS transistor has a gate, a drain, and a source. The gate is coupled to the control signal. The drain is coupled to a constant current source such that the constant current flows through the second MOS transistor when the control signal is ON. The source is coupled to the source of the first MOS transistor. The first and second MOS transistors are operating in the linear region when the control signal is ON. Finally, a means to compare the first MOS transistor drain voltage and the second MOS transistor drain voltage is provided.

Claims

1. A current sense circuit comprising:

a first MOS transistor having a gate, a drain, and a source wherein said gate is coupled to a control signal and wherein said drain is coupled to a load such that a load current flows through said first MOS transistor when said control signal is ON;

a second MOS transistor having a gate, a drain, and a source wherein said gate is coupled to said control signal, wherein said drain is coupled to a constant current source such that said constant current flows through said second MOS transistor when said control signal is ON, wherein said source is coupled to said source of said first MOS transistor, and wherein said first and second MOS transistors are operating in the linear region when said control signal is ON; and

a means to compare said first MOS transistor drain voltage and said second MOS transistor drain voltage.

2. The circuit according to claim 1 wherein said first MOS transistor has a first width-to-length ratio, wherein said second MOS transistor has a second width-to length ratio, wherein the quotient of said first width-to-length ratio divided by said second width-to-length ratio is a sense ratio, and wherein said first MOS transistor drain voltage exceeding said second MOS transistor drain voltage implies said load current value exceeds the product of said sense ratio multiplied by said constant current.

3. The circuit according to claim 1 wherein said sense ratio is between about 1 and 10,000.

4. The circuit according to claim 2 further comprising a means to turn OFF said control signal when said first MOS transistor drain voltage exceeds said second MOS transistor drain voltage.

5. The circuit according to claim 1 wherein said first and second MOS transistors comprise one of the group containing:

NMOS transistors and PMOS transistors.

6. The circuit according to claim 1 wherein said constant current source value is adjustable.

7. The circuit according to claim 1 wherein said first and second MOS transistors have common length, common physical orientation, and are formed on a common substrate.

8. The circuit according to claim 1 wherein said means of comparing comprises a comparitor.

9. A current sense circuit comprising:

a first MOS transistor having a gate, a drain, and a source wherein said gate is coupled to a control signal, wherein said drain is coupled to a load such that a load current flows through said first MOS transistor when said control signal is ON, and wherein said first MOS transistor has a first width-to-length ratio;

a second MOS transistor having a gate, a drain, and a source wherein said gate is coupled to said control signal,

wherein said drain is coupled to a constant current source such that said constant current flows through said second MOS transistor when said control signal is ON, wherein said source is coupled to said source of said first MOS transistor, wherein said first and second MOS transistors are operating in the linear region when said control signal is ON, wherein said second MOS transistor has a second width-to-length ratio, and wherein the quotient of said first width-to-length ratio divided by said second width-to-length ratio is a sense ratio; and

a means to compare said first MOS transistor drain voltage and said second MOS transistor drain voltage wherein said first MOS transistor drain voltage exceeding said second MOS transistor drain voltage implies said load current value exceeds the product of said sense ratio multiplied by said constant current.

10. The circuit according to claim 9 wherein said sense ratio is between about 1 and 10,000.

11. The circuit according to claim 9 further comprising a means to turn OFF said control signal when said first MOS transistor drain voltage exceeds said second MOS transistor drain voltage.

12. The circuit according to claim 9 wherein said first and second MOS transistors comprise one of the group containing:

NMOS transistors and PMOS transistors.

13. The circuit according to claim 9 wherein said constant current source value is adjustable..

14. The circuit according to claim 9 wherein said first and second MOS transistors have common length, common physical orientation, and are formed on a common substrate.

15. The circuit according to claim 9 wherein said means of comparing comprises a comparitor.

16. A current sense circuit comprising:

a first NMOS transistor having a gate, a drain, and a source wherein said gate is coupled to a control signal, wherein said drain is coupled to a load such that a load current flows through said first NMOS transistor when said control signal is ON, and wherein said first NMOS transistor has a first width-to-length ratio;

a second NMOS transistor having a gate, a drain, and a source wherein said gate is coupled to said control signal, wherein said drain is coupled to a constant current source such that said constant current flows through said second NMOS transistor when said control signal is ON, wherein;

said source is coupled to said source of said first NMOS transistor, wherein said first and second MOS transistors are operating in the linear region when said control signal is ON, wherein said second NMOS transistor has a second width-to-length ratio, and wherein the quotient of said first width-to-length ratio divided by said second width-to-length ratio is a sense ratio; and

a comparitor to compare said first NMOS transistor drain voltage and said second NMOS transistor drain voltage wherein said first NMOS transistor drain voltage exceeding said second NMOS transistor drain voltage implies said load current value exceeds the product of said sense ratio multiplied by said constant current.

17. The circuit according to claim 16 wherein said sense ratio is between about 1 and 10,000.

18. The circuit according to claim 16 further comprising a means to turn OFF said control signal when said first NMOS transistor drain voltage exceeds said second NMOS transistor drain voltage.

19. The circuit according to claim 16 wherein said constant current source value is adjustable.

20. The circuit according to claim 16 wherein said first and second NMOS transistors have common length, common physical orientation, and are formed on a common substrate.