Printed circuit assembly having integrated resistors for terminating data and control lines of a host-peripheral interface

• US 6,480,020 B1
• Filed: 05/18/1999
• Issued: 11/12/2002
• Est. Priority Date: 05/18/1999
• Status: Active Grant

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Mathur, Sanjay S., Wilkins, Virgil V., Jung, Hoover K.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/314,277
• Time in Patent Office: 1,274 Days
• Field of Search: 326/26-28, 326/30, 326/82, 326/83, 326/86
• US Class Current: 326/30
• CPC Class Codes: H05K 1/0246 Termination of transmission lines
• CPC Class Codes: H05K 2201/09236 Parallel layout
• CPC Class Codes: H05K 2201/10022 Non-printed resistor
• CPC Class Codes: H05K 2201/1053 Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

Abstract

A printed circuit board assembly (PCBA) includes first and second integrated-circuit terminals and first and second connector terminals. A first transmission line transmits a data signal and a second transmission line transmits a clocking signal. The PCBA includes integrated circuitry comprising first and second pads, a first digital circuit for propagating the data signal through the first pad and a second digital circuit for propagating the clocking signal through the second pad. The first transmission line includes a first integrated-circuit conductive path including a first series-connected integrated circuit resistive element and a first printed-circuit conductive path. The second transmission line includes a second integrated-circuit conductive path including a second integrated-circuit resistive element and a second printed-circuit conductive path. The first resistive element has a first ohmic value, the second resistive element has a second ohmic value, the first printed circuit conductive path has a third ohmic value and the second printed circuit conductive path has a fourth ohmic value. The ratio of the third to the first ohmic value is such that the first ohmic value is in excess of an order of magnitude greater than the third ohmic value and the ratio of the fourth to the second ohmic value is such that the second ohmic value is in excess of an order of magnitude greater than the fourth ohmic value. The ratio of the first to the second ohmic value is substantially less than the ratio of the third ohmic value to the first ohmic value.

Claims

1. A printed circuit board assembly that is plug compatible with a host-peripheral interface via which digital data are synchronously transmitted at a data rate via conductive paths that exhibit transmission-line characteristics at the data rate, the printed circuit board assembly comprising:

a first integrated-circuit terminal and a first connector terminal;

a first transmission line for transmission of a data signal;

a second integrated-circuit terminal and a second connector terminal;

a second transmission line for transmission of a clocking signal;

integrated circuitry including;

a first pad and a second pad;

a first digital circuit for propagating the data signal through the first pad;

a second digital circuit for propagating the clocking signal through the second pad;

the first transmission line including;

a first integrated-circuit conductive path including a first integrated-circuit resistive element connected in series between the first pad and the first digital circuit; and

a first printed-circuit conductive path;

the second transmission line including;

a second integrated-circuit conductive path including a second integrated-circuit resistive element; and

a second printed-circuit conductive path;

the first integrated-circuit element having a first ohmic value;

the second integrated-circuit element having a second ohmic value;

the first printed circuit conductive path having a third ohmic value, the ratio of the third ohmic value to the first ohmic value being such that the first ohmic value is in excess of an order of magnitude greater than the third ohmic value;

the second printed circuit conductive path having a fourth ohmic value, the ratio of the fourth ohmic value to the second ohmic value being such that the second

ohmic value is in excess of an order of magnitude greater than the fourth ohmic value;

the ratio of the first ohmic value to the second ohmic value being substantially less than the ratio of the third ohmic value to the first ohmic value.

2. The printed circuit board assembly of claim 1, wherein the first integrated resistive element comprises at least one first n-type portion and at least one first p-type portion, the first n-type portion including material doped with an n-type dopant and the first p-type portion including material doped with a p-type dopant, the first n-type portion and the first p-type portion being electrically coupled to one another via a first metal layer.

3. The printed circuit board assembly of claim 2, wherein the first n-type portion comprises a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled to the first n-type layer by the first metal layer.

4. The printed circuit board assembly of claim 1, wherein the second integrated resistive element comprises at least one second n-type portion and at least one second p-type portion, the second n-type portion including material doped with an n-type dopant and the second p-type portion including material doped with a p-type dopant, the second n-type portion and the second p-type portion being electrically coupled to one another via a second metal layer.

5. The printed circuit board assembly of claim 4, wherein the second n-type portion comprises a third n-type layer including material doped with the n-type dopant and a fourth n-type layer including material doped with the n-type dopant, the fourth n-type layer being electrically coupled to the third n-type layer by the second metal layer.

6. The printed circuit board assembly of claim 1,wherein each of the first and second ohmic values is selected in a range between about 30 Ω

and about 90 Ω

.

7. The printed circuit board assembly of claim 1, wherein the integrated circuitry implements an ATA Ultra DMA protocol and wherein each of the first and second integrated circuit resistive elements includes at least one portion doped with an n-type dopant and at least one other portion doped with a p-type dopant.

8. An integrated circuit for a host-peripheral interface via which digital data are synchronously transmitted at a data rate via conductive paths that exhibit transmission-line characteristics at the data rate, the integrated circuit comprising:

a first integrated-circuit terminal and a first connector terminal;

a first transmission line for transmission of a data signal;

a second integrated-circuit terminal and a second connector terminal;

a second transmission line for transmission of a clocking signal;

a first pad and a second pad;

a first digital circuit for propagating the data signal through the first pad;

a second digital circuit for propagating the clocking signal through the second pad;

the first transmission line including a first integrated-circuit conductive path including a first integrated-circuit resistive element connected in series between the first pad and the first digital circuit, the first integrated resistive element comprising at least one first n-type portion and at least one first p-type portion, the first n-type portion including material doped with an n-type dopant and the first p-type portion including material doped with a p-type dopant, the first n-type portion and the first p-type portion being electrically coupled to one another via a first metal layer, the first n-type portion comprising a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled to the first n-type layer by the first metal layer;

the second transmission line including a second integrated-circuit conductive path including a second integrated-circuit resistive element;

the first integrated-circuit element having a first ohmic value and the second integrated-circuit element having a second ohmic value, each of the first and second ohmic values being of a magnitude that substantially matches a characteristic impedance of the conductive paths at the data rate.

9. The integrated circuit of claim 8, wherein the magnitude of each of the first and second integrated circuit resistive elements is selected between about half and about double the characteristic impedance of the conductive paths at the data rate.

10. The integrated circuit of claim 8 wherein the first and second integrated circuit resistive elements are formed from an active structure.

11. The integrated circuit of claim 10 wherein the active structure is a FET.

12. The integrated circuit of claim 8, wherein the second integrated resistive element comprises at least one second n-type portion and at least one second p-type portion, the second n-type portion including material doped with an n-type dopant and the second p-type portion including material doped with a p-type dopant, the second n-type portion and the second p-type portion being electrically coupled to one another via a second metal layer.

13. The integrated circuit of claim 12, wherein the second n-type portion comprises a third n-type layer including material doped with the n-type dopant and a fourth n-type layer including material doped with the n-type dopant, the fourth n-type layer being electrically coupled to the third n-type layer by the second metal layer.

14. The integrated circuit of claim 8, wherein each of the first and second ohmic values is selected in a range between about 30 Ω

and about 90 Ω

.

15. The integrated circuit of claim 8, wherein the integrated circuit implements an ATA Ultra DMA protocol and wherein each of the first and second integrated circuit resistive elements includes at least one portion doped with an n-type dopant and at least one other portion doped with a p-type dopant.

16. A printed circuit board assembly comprising:

an integrated-circuit terminal and a connector terminal;

a printed-circuit conductive path connecting the integrated circuit terminal and the connector terminal;

integrated circuitry including;

a pad;

a digital circuit for propagating the signal through the pad;

an integrated-circuit conductive path connecting the pad to the integrated circuit terminal, the integrated circuit conductive path including an integrated-circuit resistive element connected in series between the pad and the digital circlet, the integrated-circuit resistive element including at least one first portion doped with an n-type dopant electrically coupled to and separated from at least one second portion doped with a p-type dopant, the first portion doped with the n-type dopant comprising a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled with first n-type layer via a metal layer.

17. An integrated circuit for a host-peripheral interface via which digital data are synchronously transmitted at a data rate via Conductive paths that exhibit transmission-line characteristics at the data rate, the integrated circuit comprising:

a first integrated-circuit terminal and a first connector terminal;

a first transmission line for transmission of a data signal;

a second integrated-circuit terminal and a second connector terminal;

a second transmission line for transmission of a clocking signal;

a first pad and a second pad;

a first digital circuit for propagating the data signal through the first pad;

a second digital circuit for propagating the clocking signal through the second pad;

the first transmission line including a first integrated-circuit conductive path including a first integrated-circuit resistive element connected in series between the first pad and the first digital circuit;

the second transmission line including a second integrated-circuit conductive path including a second integrated-cicuit resistive element, the second integrated resistive element comprising at least one second n-type portion and at least one second p-type portion, the second n-type portion including material doped with an n-type dopant and the second p-type portion including material doped with a p-type dopant, the second n-type portion and the second p-type portion being electrically coupled to one another via a second metal layer, the second n-type portion comprising a third n-type layer including material doped with the n-type dopant and a fourth n-type layer including material doped with the n-type dopant, the fourth n-type layer being electrically coupled to the third n-type layer by the second metal layer;

the first integrated-circuit element having a first ohmic value and the second integrated-circuit element having a second ohmic value, each of the first and second ohmic values being of a magnitude that substantially matches a characteristic impedance of the conductive paths at the data rate.

18. The integrated circuit of claim, 17, wherein each of the first and second ohmic values is selected in a range between about 30 Ω

and about 90 Ω

.

19. he integrated circuit of claim 17, wherein the integrated circuit implements an ATA Ultra DMA protocol and wherein each of the first and second integrated circuit resistive elements includes at least one portion doped with an n-type dopant and at least one other portion doped with a p-type dopant.

20. The integrated circuit of claim 17, wherein the first and second integrated circuit resistive elements are formed from an active structure.

21. The integrated circuit of claim 20 wherein the active structure is a FET.

22. The integrated circuit of claim 17, wherein the magnitude of each of the first and second integrated circuit resistive elements is selected between about half and about double the characteristic impedance of the conductive pats at the data rate.

23. The integrated circuit of claim 17, wherein the first integrated resistive element comprises at least one first n-type portion and at least one first p-type portion, the first n-type portion including material doped with an n-type dopant and the fist p-type portion including material doped with a p-type dopant, the first n-type portion and the first p-type portion being electrically coupled to one another via a first metal layer.

24. The integrated circuit of claim 23, wherein the first n-type portion comprises a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled to the first n-type layer by the first metal layer.