Active load circuit, and operational amplifier and comparator having the same

• US 6,480,069 B2
• Filed: 03/02/2001
• Issued: 11/12/2002
• Est. Priority Date: 09/14/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Yasukouchi, Katsuyuki
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Nguyen, Khanh Van
• Application Number:
  US09/796,549
• Publication Number:
  US 20020030542A1
• Time in Patent Office: 620 Days
• Field of Search: 330/257, 330/288, 323/325, 323/316
• US Class Current: 330/288
• CPC Class Codes: H03F 2203/45644 the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/3023 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

An active load circuit is provided, which is suitable for achieving an operational amplifier circuit, and which may cope with both output current capability and lower consumption current, with less offset, and may be capable of operating at higher speed in case of transient response. The active load circuit is comprised of MOS transistors Tr1 and Tr5 for forming a first current mirror circuit, MOS transistors Tr11 and Tr3 for forming a second current mirror circuit, and resistors R1 and R2. The sources of output transistors Tr5 and Tr11 of respective current mirror circuits are connected to the sources of input transistors Tr3 and Tr1 of the other current mirror circuits and then to the resistors R1 and R2. When the differential current component in the differential input stage becomes larger at the time of transient response of the operational amplifier, the bias current flowing through the next and following stages may be amplified, so that the high speed response characteristics in the transient response of the operational amplifier may be improved.

Claims

1. An active load circuit, comprising:

first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors;

second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors;

first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and

second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential,

wherein the first and second impedance circuits have first and second MOS transistors, respectively, and

wherein the gate terminal of the first MOS transistor is connected to second input terminal of the second current mirror circuit, and the gate terminal of the second MOS transistor is connected to first input terminal of the first current mirror circuit.

2. An active load circuit set forth in claim 1, wherein the first impedance circuit has a first resistor element, and the second impedance circuit has a second resistor element.

3. An active load circuit set forth in claim 1,

wherein the first impedance circuit has a first active element, and the second impedance circuit has a second active element, and

wherein the first and second active elements are impedance controlled such that the impedance of the first active element increases or decreases in response to the increase or decrease of the input current input to the second current mirror circuit, and the impedance of the second active element increases or decreases in response to the increase or decrease of the input current input to the first current mirror circuit.

4. An active load circuit set forth in claim 1, wherein the first and second current mirror circuits are formed of MOS transistors.

5. An active load circuit set forth in claim 1, wherein the first and second current mirror circuits are formed of bipolar transistors.

6. An operational amplifier comprising the active load circuit set forth in claim 1 for the active load circuit in the input differential stage.

7. A comparator comprising the active load circuit set forth in claim 1 for the active load circuit in the input differential stage.

8. An operational amplifier, comprising:

an active load circuit at the input differential stage, the active load circuit comprising;

first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors;

second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors;

first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and

second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential,

wherein in the active load circuit, the first and second impedance circuits have first and second MOS transistors, respectively, and

wherein the gate terminal of the first MOS transistor is connected to the second input terminal of the second current mirror circuit, and the gate terminal of the second MOS transistor is connected to the first input terminal of the first current mirror circuit.

9. An operational amplifier set forth in claim 8, wherein in the active load circuit, the first impedance circuit has a first resistor element, the second impedance circuit has a second resistor element.

10. An operational amplifier set forth in claim 8,

wherein in the active load circuit, the first impedance circuit has a first active element, and the second impedance circuit has a second active element, and

wherein the first and second active elements are impedance controlled such that the impedance of the first active element increases or decreases in response to the increase or decrease of the input current input to the second current mirror circuit, and the impedance of the second active element increases or decreases in response to the increase or decrease of the input current input to the first current mirror circuit.

11. An operational amplifier set forth in claim 8 wherein in the active load circuit, the first and second current mirror circuits are formed of MOS transistors.

12. An operational amplifier set forth in claim 8, wherein in the active load circuit, the first and second current mirror circuits are formed of bipolar transistors.

13. An active load circuit, comprising:

first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors;

second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors;

first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and

second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential,

wherein the first and second impedance circuits have first and second junction FETs, respectively, and

wherein the gate terminal of the first junction FET is connected to second input terminal of the second current mirror circuit, and the gate terminal of the second junction FET is connected to first input terminal of the first current mirror circuit.

14. An operational amplifier, comprising:

an active load circuit at the input differential stage, the active load circuit comprising;

first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors;

second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors;

first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and

second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential,

wherein in the active load circuit, the first and second impedance circuits have first and second junction FETs, respectively, and

wherein the gate terminal of the first junction FET is connected to the second input terminal of the second current mirror circuit, and the gate terminal of the second junction FET is connected to the first input terminal of the first current mirror circuit.