Autonomous hardwired tracking loop coprocessor for GPS and WAAS receiver
DCFirst Claim
1. An autonomous hardwired tracking loop (HWTL) integrated circuit comprising:
- a HWTL coprocessor coupled to receive an IF signal from a correlator engine, the HWTL coprocessor providing radio signal processing comprising data tracking or acquisition processing on the IF signal to generate HWTL processed data for further radio receiver processing operations by a CPU.
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Abstract
An autonomous Hardwired Tracking Loop (HWTL) ASIC comprising a HWTL coprocessor provided for implementing most of the receiver processing function for data acquisition and tracking functions of a radio receiver system in dedicated hardware. With the expanded functionality provided by an HWTL coprocessor in the autonomous HWTL ASIC, the interruption of CPU performing the navigation processing is significantly reduced to thereby maximize throughput and minimize power burden on the microprocessor. In the preferred embodiment, the HWTL ASIC also comprises the CPU and a correlator, wherein the correlator provides the high rate greater than approximately 1 KHz signal processing operations, the HWTL coprocessor providing the data acquisition and tracking (medium frequency signal processing) operations, and the CPU thereby freed to provide more bandwidth for lower frequency processing, i.e., navigation and non-radio receiver operations, such as user applications, processing requiring CPU intervention at approximately 10 Hz or less CPU processing rate.
129 Citations
36 Claims
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1. An autonomous hardwired tracking loop (HWTL) integrated circuit comprising:
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a HWTL coprocessor coupled to receive an IF signal from a correlator engine, the HWTL coprocessor providing radio signal processing comprising data tracking or acquisition processing on the IF signal to generate HWTL processed data for further radio receiver processing operations by a CPU. - View Dependent Claims (2, 3, 4, 5, 6)
a track state module (TRKSTATE) that initiates a set of state machine operations, and also provides a plurality of functional control signals of the HWTL coprocessor comprising one or more select and enable lines; and
an ALU coupled to the TRKSTATE module to receive the one or more select and enable signal to provide a plurality of data path calculations for tracking, the ALU is also coupled to the one or more on-board memory components for retrieving and storing a set of processed data;
a track support module (TRKSUP) comprising a set of assorted logic for supporting signal processing and acquisition operations;
a track CPU module (TRKCPU) for handling interface to the CPU via a bus; and
a track address generator (TRKADDRGEN) for generating one or more control lines and addresses for accessing the one or more on-board memory components and the Correlator engine.
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5. The HWTL integrated circuit of claim 1, wherein the HWTL coprocessor acquires, tracks and demodulates WAAS data.
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6. The HWTL integrated circuit of claim 1, wherein the HWTL coprocessor provides a half millisecond mode operation of the hardwired tracking loop to support WAAS bitsync and data demodulation and to support reacquisition ½
- millisecond coherent dwells.
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7. An autonomous hardwired tracking loop (HWTL) radio receiver system comprising:
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a correlator engine, the correlator engine receives an IF signal and provides correlation operations to generate a correlated data output;
a CPU; and
a HWTL coprocessor coupled between the correlator engine and the CPU to direct passage of data via one or more on-board memory components to the correlator engine or the CPU, wherein the one or more on-board memory components comprises storing a set of parameters associated with data tracking and acquisition operations. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
a track state module (TRKSTATE) that initiates a set of state machine operations, and also provides a plurality of functional control signals of the HWTL coprocessor comprising one or more select and enable lines; and
an ALU coupled to the TRKSTATE module to receive the one or more select and enable signal to provide a plurality of data path calculations for tracking, the ALU is also coupled to the one or more on-board memory components for retrieving and storing a set of processed data;
a track support module (TRKSUP) comprising a set of assorted logic for supporting signal processing and acquisition operations;
a track CPU module (TRKCPU) for handling interface to the CPU via a bus; and
a track address generator (TRKADDRGEN) for generating one or more control lines and addresses for accessing the one or more on-board memory components and the Correlator engine.
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12. The HWTL radio receiver of claim 7, wherein the HWTL coprocessor acquires, tracks and demodulates WAAS data.
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13. The HWTL radio receiver of claim 7, wherein the HWTL coprocessor is coupled to the CPU to provide the HWTL processed data to the CPU, wherein the CPU provides navigation and other non-radio receiver processing.
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14. The HWTL radio receiver of claim 7, wherein the HWTL coprocessor provides signal processing operations in a range from approximately 10 Hz to 1 KHz processing rate.
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15. An autonomous hardwired tracking loop method (HWTL method) for a radio receiver system having a correlator, a CPU, and a HWTL coprocessor, wherein the HWTL method comprises:
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providing signal processing functions requiring greater than 1 KHz frequency rate by the correlator;
providing receiver processing comprising data acquisition and tracking function processing by the HWTL coprocessor; and
providing navigation and non-radio receiver operations by the CPU. - View Dependent Claims (16, 17)
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18. An apparatus for acquiring and tracking signals received from a plurality of GPS transmitters, comprising:
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an engine for correlating the signals received from the plurality of GPS transmitters; and
a subsystem communicatively coupled to the engine, the subsystem configured to acquired and track the correlated signals, the subsystem including;
a subsystem processor, implementing at least one software module that acquires and track the correlated signals according to instructions stored in a memory communicatively coupled to the processor, wherein the instructions include at least one operation implemented in a circuit module. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
a time counter shared by all of a plurality of channels;
a channel specific time counter for each of the plurality of channels;
a code tap counter;
a frequency bin counter;
an integrated counter;
a dump counter;
a shift register and counter;
an up/down counter;
a code step counter; and
a doppler step counter.
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25. The apparatus of claim 18, wherein the operations include at least one operation for accessing, updating, or storing data in stored in a data demodulator shift register.
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26. The apparatus of claim 18, wherein the operations include at least one operation for accessing, updating, or storing data in stored in a plurality of histogram bins.
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27. The apparatus of claim 18, wherein the operations include at least one operation for setting and resetting a flag selected from the group comprising:
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a bit synchronization flag; and
a track mode flag.
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28. The apparatus of claim 18, wherein the operations include at least one operation for accessing an indicator selected from the group comprising:
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a code lock indicator; and
a costas lock indicator.
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29. The apparatus of claim 18, further comprising a navigation processor.
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30. The apparatus of claim 29, wherein the navigation processor and the engine are implemented in the same integrated circuit.
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31. The apparatus of claim 30, wherein the navigation processor, the subsystem processor and the engine are implemented in the same integrated circuit.
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32. The apparatus of claim 18, wherein the subsystem processor implements a plurality of hierarchically organized software modules, including:
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a first software module, communicatively coupled to the engine;
a first set of software modules, each of the software modules operating under control of the first software module.
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33. The apparatus of claim 32, wherein the first software module is activated by the engine.
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34. The apparatus of claim 33, wherein the first software module is activated by an interrupt signal from the engine.
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35. The apparatus of claim 32, wherein the first set of software modules includes:
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an acquisition software module for acquiring and reacquiring the signals received from the plurality of GPS transmitters;
a tracking software module for tracking the signals received from the plurality of GPS transmitters.
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36. The apparatus of claim 35, wherein the first set of software modules further comprises an initialization software module for initializing the first software module and the second software module.
Specification