Multi-function controller and method for a computer graphics display system

• US 6,480,198 B2
• Filed: 01/10/2000
• Issued: 11/12/2002
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: S3 Graphics Co., Ltd. (HTC Corporation)
• Original Assignee: S3 Graphics Co., Ltd. (HTC Corporation)
• Inventors: Kang, Dan C.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/481,371
• Publication Number:
  US 20010012015A1
• Time in Patent Office: 1,037 Days
• Field of Search: 345/302, 345/502, 345/507-509, 345/512, 345/513, 345/519-521, 345/526, 345/531, 345/541, 345/542, 345/557, 345/536, 345/532, 710/100, 710/126-129
• US Class Current: 345/519
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A multi-function controller in a computer graphics system performs the functions of a graphics processor, a video processor, a system memory controller, a cache controller, and a PCI bridge. The multi-function controller is connected to the host bus of the computer graphics display system to maximize performance. A graphics frame buffer and a system memory are combined into a unified system memory, which is controlled by and coupled to the multi-function controller.

Claims

1. A controller for use in a computer graphics system having a system memory and a CPU coupled to a host bus, the controller comprising:

a unified graphics controller comprised of a graphics processor coupled to a system memory controller that controls the system memory, the unified graphics controller being coupled to the system memory and a dedicated CPU-data bus that carries data between the CPU and the unified graphics controller, the CPU-data bus being directly coupled to the host bus whereby the graphics processor receives data directly from the CPU; and

a bus bridge that controls transfer of at least some of the information on a bus in the computer graphics system, receives address and control information from the CPU through a CPU-control bus coupled to the host bus, and sends address and control information to the unified graphics controller though a communications link coupled to the unified graphics controller,

wherein all address control information for the unified graphics controller from various components in the computer graphics system are received by the unified graphics controller from the bus bridge through the communications link.

2. The controller of claim 1 wherein the graphics processor is a video processor.

3. The controller of claim 1 further comprising a cache controller for controlling a cache in the computer graphics system, the cache controller coupled to the graphics processor.

4. The controller of claim 1 wherein the unified graphics controller is integrated into a single chip and the bus bridge and the cache controller form a combined bus bridge/cache controller integrated into a single chip.

5. The controller of claim 4 wherein the unified graphics controller and the combined bus bridge/cache controller form a multi-function controller integrated into a single chip.

6. The controller of claim 1 wherein the system memory contains graphics data and non-graphics data.

7. The controller of claim 1 further comprising a plurality of data buffers coupled to the system memory controller for storing data traveling between the system memory and a remainder of the computer graphics system.