Method and system for testing RAMBUS memory modules

• US 6,480,799 B2
• Filed: 08/31/2001
• Issued: 11/12/2002
• Est. Priority Date: 08/26/1998
• Status: Expired due to Term

• Current Assignee: Neosem, Inc., Tanisys Technology, Inc. (Spirox Corporation)
• Original Assignee: Tanisys Technology, Inc. (Spirox Corporation)
• Inventors: Hunter, Paul R.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Raymond, Edward
• Application Number:
  US09/943,721
• Publication Number:
  US 20020032537A1
• Time in Patent Office: 438 Days
• Field of Search: 702/117, 702/118, 702/119, 710/101, 710/107, 710/52, 713/1, 713/2, 711/1, 711/2, 711/5, 711/101, 711/104, 711/202, 711/211, 711/215, 711/218, 703/13
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A system and method for testing a RIMM loaded with RDRAM integrated circuits generates and reads test transaction data with a test transaction engine, such as a microprocessor-based memory tester. A RIMM adapter interfaces with the test transaction engine and the RIMM under test to communicate test data, including test write, address, control and read data. A comparison of test read data returned to the test transaction engine from the RIMM against predetermined values allows a determination of the operational status of the RIMM. The RIMM adapter is embodied as an ASIC with plural FIFO circuits interfaced between the test transaction engine and a channel controller and RAC. The FIFOs reconcile differences in timing between generation and return of test data and demands by the RAC and channel controller. Separate read and write data paths between the test transaction engine and ASIC support improved rates of data transfer. The test transaction engine provides full speed test transactions by using instruction data to generate test data with FPGAs.

Claims

1. A system for testing a RAMBUS memory module, the system comprising:

an application specific integrated circuit for communicating test data with a RAMBUS memory module through a RAMBUS channel, the application specific integrated circuit comprising;

a RAMBUS ASIC Channel cell for providing test data to the RAMBUS channel and accepting test data from the RAMBUS channel; and

a channel controller interfaced with the RAMBUS ASIC Channel cell, the channel controller for controlling the writing and reading of test data by the RAMBUS ASIC Channel cell; and

a test transaction engine interfaced with the application specific integrated circuit through an adapter connector, the test transaction engine comparing test data written to the RAMBUS memory module with test data read from the RAMBUS memory module to determine the operation of the RAMBUS memory module.

2. The system of claim 1 further comprising at least one first-in-first-out circuit associated with the application specific integrated circuit and interfaced with the channel controller, the first-in-first-out circuit for accepting test data from the test transaction engine and providing test data to the test transaction engine.

3. The system of claim 1 wherein the application specific integrated circuit further comprises:

a write first-in-first-out circuit for accepting test write data from the test transaction engine;

a read first-in-first-out circuit for providing test read data to the test transaction engine; and

an address first-in-first-out circuit for accepting test addresses from the test transaction engine.

4. The system of claim 3 wherein the address first-in-first-out circuit further accepts test control information from the test transaction engine.

5. The system of claim 4 wherein the application specific integrated circuit further comprises a control interface circuit interfaced with the channel controller, the control interface circuit for accepting test control data from the test transaction engine.

6. The system of claim 4 wherein the application specific integrated circuit further comprises registers interfaced with the channel controller, the registers for accepting test transaction commands for modifying operational characteristics of the channel controller.

7. The application specific integrated circuit according to claim 3 wherein the read first-in-first-out circuit provides 144 bit wide read test data.

8. The application specific integrated circuit according to claim 3 wherein the write first-in-first-out circuit accepts first and second 144 bit wide datums for each test data transaction.

9. The application specific integrated circuit according to claim 3 wherein the address first-in-first-out circuit accepts 35 bit address information for each RIMM transaction.

10. The application specific integrated circuit according to claim 3 wherein the address first-in-first-out circuit further accepts 5 bit control information for each RIMM transaction.

11. A system for testing a RIMM, the system comprising:

a test transaction engine that writes test transaction data for storage on the RIMM, reads the test transaction data stored on the RIMM and compares the write test transaction data with the read test transaction data to test the operation of the RIMM;

A RIMM adapter having RAMBUS ASIC channel cell and a channel controller incorporated in an application specific integrated circuit, the RIMM adapter for communicating test transaction data between the test transaction engine and the RIMM; and

a connector that interfaces the test transaction engine and the RIMB adapter.

12. The system according to claim 11 wherein the test transaction data comprises test address, control and write data.

13. The system according to claim 11 wherein the test transaction engine provides write data over a write data path of the connector and receives read data over a read data path of the connector, the write and read data paths being separate data paths of the connector.

14. The system according to claim 11 wherein the test transaction engine comprises:

instruction memory for storing test transaction instructions;

a write generate engine interfaced with the instruction memory, the write generate engine for generating test write data from the test transaction instructions; and

an address control generate engine interfaced with the instruction memory, the address control generate engine for generating test address data and test control data from the transaction instructions.

15. The system according to claim 14 further comprising a read compare engine for accepting test read data from the RIMM adapter and comparing the test read data against test write data to determine RIMM results.

16. The system according to claim 15 wherein the read compare engine comprises a write generate engine for generating test write data from the test transaction instructions.

17. The system according to claim 15 wherein the write generate engine and read compare engine interface with the RIMM adapter through separate data paths.

18. The system according to claim 15 wherein the address control generate engine comprises:

at least one field programmable gate arrays, the field programmable gate array having

at least one arithmetic logic unit for generating test data; and

plural interleaved banks of plural registers, the registers for providing test address or control data to the RIMM adapter.

19. The system according to claim 15 wherein the read compare engine comprises a field programmable gate array.

20. The system according to claim 15 wherein the write generate engine comprises a field programmable gate array.

21. The system according to claim 15 further comprising:

a write first-in-first-out circuit interfacing the write generate engine and the RIMM adapter; and

an address first-in-first-out circuit interfacing the address control generate engine and the RIMM adapter.

22. The system according to claim 21 further comprising an address cross-bar switch interfaced with the address first-in-first-out circuit for sequencing test addresses generated by the address control generate engine.

23. A method for testing a RIMM comprising the steps of:

generating test transaction information with a test transaction engine;

providing the test transaction information to a RIMM adapter from the test transaction engine through a connector;

storing the test transaction information on the RIMM;

reading the stored test transaction information from the RIMM through the RIMM adapter;

providing the stored test transaction information from the RIMM adapter to the test transaction engine through the connector; and

comparing the test transaction information read from the RIMM against predetermined results to determine the operational status of the RIMM.

24. The method according to claim 23 wherein the RIMM adapter comprises an application specific integrated circuit having a RAMBUS ASIC channel cell and a channel controller.

25. The method according to claim 23 wherein the test transaction information comprises test write data.

26. The method according to claim 23 wherein the generating step comprises providing instructions to a write generate engine to algorithmically generate test write data.

27. The method according to claim 23 wherein the providing the test transaction data to the RIMM step further comprises the steps of:

providing the test write data to the channel controller; and

using the channel controller to direct the RAMBUS ASIC channel cell to send the test write data to the RIMM.

28. The method according to claim 26 wherein the comparing step further comprises the step of generating read compare test data with the instructions and a read compare engine for comparison with the data read from the RIMM.

29. The method according to claim 27 wherein the test transaction information further comprises test address information and test control information, the using the channel controller step further comprising the step of using the channel controller to store the test write data on the RIMM according to the test address information and test control information.

30. The method according to claim 27 further comprising the step of providing predetermined test write data to the RIMM by bypassing the channel controller.

31. The method according to claim 29 wherein the providing test transaction information step further comprises the steps of:

providing test write data to a write first-in-first-out circuit interfaced with the channel controller;

providing the test address information to an address first-in-first-out circuit interfaced with the channel controller;

providing the test control information to a control first-in-first-out circuit interfaced with the channel controller; and

accessing the write, address and control first-in-first-out circuits with the channel controller to provide the test write data to the RIMM.

32. The method according to claim 23 wherein the test transaction information is provided to the RIMM adapter and read from the RIMM adapter through separate paths of the connector.