Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus

• US 6,480,929 B1
• Filed: 10/31/1998
• Issued: 11/12/2002
• Est. Priority Date: 10/31/1998
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mergard, Jim, Gauthier, Lloyd W., Russell, Richard G., Godfrey, Gary M.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US09/184,270
• Time in Patent Office: 1,473 Days
• Field of Search: 711/154, 711/168, 711/102-105, 365/185.08, 710/313
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A system provides pseudo-concurrency for a volatile memory and a non-volatile memory on a same data bus. In one system embodiment, the volatile memory is coupled to its own address bus, and the non-volatile memory is coupled to its own address bus. In another system embodiment, the volatile memory and non-volatile memory are coupled to a multiplexed address bus. Concurrent with an access cycle to the volatile memory, the non-volatile memory may be precharged. After the access cycle to the volatile memory, a data cycle to a non-volatile memory may be executed. Concurrent with an access cycle to the non-volatile memory, the volatile memory may be precharged. After the access cycle to the non-volatile memory, a data cycle to the volatile memory may be executed.

Claims

1. A system for operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising:

a data bus;

a processor coupled to the data bus;

a volatile memory coupled to the data bus;

a non-volatile memory coupled to the data bus;

a first address bus coupled to the volatile memory; and

a second address bus coupled to the non-volatile memory.

2. The system of claim 1, further comprising:

a first control bus coupled to the volatile memory; and

a second control bus coupled to the non-volatile memory.

3. The system of claim 1, further comprising:

a bus master coupled to the data bus, the first address bus, and the second address bus.

4. The system of claim 3, wherein the bus master executes an access cycle to the volatile memory and concurrently precharges the non-volatile memory.

5. The system of claim 4, wherein the bus master executes a data cycle to the non-volatile memory after executing an access cycle to the volatile memory.

6. The system of claim 3, wherein the bus master executes an access cycle to the non-volatile memory and concurrently precharges the volatile memory.

7. The system of claim 6, wherein the bus master executes a data cycle to the volatile memory after executing an access cycle to the non-volatile memory.

8. The system of claim 6, wherein the bus master is a microcontroller.

9. The system of claim 1, wherein the data bus is a relatively fast bus.

10. A system for operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising:

a data bus;

a processor coupled to the data bus;

a volatile memory coupled to the data bus;

a non-volatile memory coupled to the data bus;

a first control bus coupled to the volatile memory;

a second control bus coupled to the non-volatile memory; and

a multiplexed address bus coupled to the volatile memory and the non-volatile memory.

11. A system for operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising:

a data bus;

a processor coupled to the data bus;

a volatile memory coupled to the data bus;

a non-volatile memory coupled to the data bus;

a bus master coupled to the data bus and the multiplexed address bus; and

a multiplexed address bus coupled to the volatile memory and the non-volatile memory,

wherein the bus master executes an access cycle to the volatile memory and concurrently precharges the non-volatile memory.

12. The system of claim 11, wherein the bus master executes a data cycle to the non-volatile memory after executing an access cycle to the volatile memory.

13. A system for operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising:

a data bus;

a processor coupled to the data bus;

a volatile memory coupled to the data bus;

a non-volatile memory coupled to the data bus;

a bus master coupled to the data bus and the multiplexed address bus; and

a multiplexed address bus coupled to the volatile memory and the non-volatile memory,

wherein the bus master executes an access cycle to the non-volatile memory and concurrently precharges the volatile memory.

14. The system of claim 13, wherein the bus master executes a data cycle to the volatile memory after executing an access cycle to the non-volatile memory.

15. A method of operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising the steps of:

providing first address information and first control information to the volatile memory;

providing second address information and second control information to the non-volatile memory concurrent with providing first address and first control information to the volatile memory;

performing a first data cycle over a data bus for the volatile memory corresponding to the first address and control information; and

performing a second data cycle over the data bus for the non-volatile memory corresponding to the second address and control information after completion of the first data cycles,

wherein the first data cycle is independent of the second data cycle.

16. The method of claim 15, wherein the first address information and the second address information are provided over the same bus.

17. The method of claim 15, wherein the first address information is provided over a first bus and the second address information is provided over a second bus.

18. A method of operating a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency, comprising the steps of:

providing first address information and first control information to the non-volatile memory;

providing second address information and second control information to the volatile memory concurrent with providing first address information and first control information to the non-volatile memory;

performing a first data cycle over a data bus for the non-volatile memory corresponding to the first address and control information; and

performing a second data cycle over the data bus for the volatile memory corresponding to the second address and control information after completion of the first data cycles,

wherein the first data cycle is independent of the second data cycle.

19. The method of claim 18, wherein the first address information and the second address information are provided over the same bus.

20. The method of claim 18, wherein the first address information is provided over a first bus and the second address information is provided over a second bus.