Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
First Claim
1. Method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement, characterized in that1.1 a plurality of cells and arithmetic units are combined to form a plurality of groups, a cache unit being assigned to each subgroup;
- 1.2 the cache units of the individual subgroups are connected, via a tree structure, to a higher level cache unit having access to the command memory in which the commands are stored;
1.3 commands are combined to form command sequences, which are always cached as a whole and transmitted between the caches;
1.4 each cache unit on the lowermost or middle level of the tree requests the required commands from the respectively assigned higher level cache unit;
1.5 a higher level cache unit sends a requested command sequence to the lower level unit if it holds the command sequences in its local memory; and
1.6 a higher level cache unit requests a requested command sequence from the respective higher level cache unit if it does not hold the command sequences in its local memory.
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Abstract
A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a group, and connecting the cache unit to a higher level unit via a tree structure. The cache unit may send requests for required commands to the higher level cache unit, which may return a command sequence including the required command, if the higher level cache unit holds the first command sequence including the required command in the higher level cache unit'"'"'s local memory.
260 Citations
12 Claims
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1. Method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement, characterized in that
1.1 a plurality of cells and arithmetic units are combined to form a plurality of groups, a cache unit being assigned to each subgroup; -
1.2 the cache units of the individual subgroups are connected, via a tree structure, to a higher level cache unit having access to the command memory in which the commands are stored;
1.3 commands are combined to form command sequences, which are always cached as a whole and transmitted between the caches;
1.4 each cache unit on the lowermost or middle level of the tree requests the required commands from the respectively assigned higher level cache unit;
1.5 a higher level cache unit sends a requested command sequence to the lower level unit if it holds the command sequences in its local memory; and
1.6 a higher level cache unit requests a requested command sequence from the respective higher level cache unit if it does not hold the command sequences in its local memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification
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- Resources
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Current AssigneeScientia Sol Mentis AG (PACT XPP Schweiz AG)
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Original AssigneePACT Informationstechnologie GmbH
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InventorsVorbach, Martin, Münch, Robert
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Primary Examiner(s)Ellis, Kevin L.
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Assistant Examiner(s)ELMORE, STEPHEN C
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Application NumberUS09/623,052Time in Patent Office672 DaysField of Search711/122, 711/125, 711/141, 711/145US Class Current711/122CPC Class CodesG06F 12/0811 with multilevel cache hiera...G06F 12/0813 with a network or matrix co...G06F 12/084 with a shared cacheG06F 15/7867 with reconfigurable archite...
