Configurable system memory map

• US 6,480,948 B1
• Filed: 06/24/1999
• Issued: 11/12/2002
• Est. Priority Date: 06/24/1999
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Virajpet, Balaji V., Popat, Kaushik L.
• Primary Examiner(s): Ellis, Kevin L.
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/339,638
• Time in Patent Office: 1,237 Days
• Field of Search: 711/202, 711/165, 711/106, 711/170, 711/134, 711/203, 711/204, 711/205, 711/206, 711/207, 711/208, 711/209, 711/210, 710/26, 713/100
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70

Abstract

A memory map for a computer system is configurable. For example a first section of the memory map (e.g., the lower address space) is configurable so that when the process accesses this section, different devices will respond depending on the memory map in effect. In one embodiment, external non-volatile memory is accessed during a first time period based on a reset memory map. After initialization, the memory may is changed to a normal one so that subsequent accesses to the same section of the memory map result in accesses to faster memory (e.g., internal SRAM). In the case where the reset vector and interrupt vectors have relatively close addresses, the configurability of the memory map allows the reset vector to be handled through accesses to non-volatile memory while interrupt vectors are handled through accesses to faster internal SRAM.

Claims

1. A computer system comprising:

a processor;

a plurality of devices accessible by said processor via one or more addresses; and

a bus controller coupled to said processor and said plurality of devices, said bus controller adapted to configure a memory map of said addresses for said computer system wherein a first device is accessible by said processor via a first subset of addresses in said memory map and a second device is accessible by said processor via a second subset of addresses in said memory map wherein

during a first time period, said bus controller configures a third subset of addresses in said memory map such that said processor accesses said first device when said processor seeks to access said third subset of said addresses; and

during a second time period, said bus controller configures the third subset of addresses in said memory map such that said processor accesses said second device when said processor seeks to access said third subset of said addresses.

2. The computer system of claim 1 wherein said first device is a non-volatile memory device.

3. The computer system of claim 2 wherein said second device is a Random-Access-Memory (RAM) device.

4. The computer system of claim 1 further comprising:

a plurality of device select lines coupled between said bus controller and said plurality of devices such that said bus controller controls which of said devices responds to accesses by said processor via said device select lines based on said memory map.

5. The computer system of claim 4 wherein said first device is a non-volatile memory device.

6. The computer system of claim 5 wherein said second device is a Random-Access-Memory (RAM) device.

7. The computer system of claim 3 further comprising:

a select signal line coupled to said bus controller, such that said bus controller selects the first device from said plurality of devices based on a signal on said select signal line.

8. The computer system of claim 7 wherein said first device is selected from non-volatile memory internal to said computer system and non-volatile memory external to said computer system based on the signal on said select signal line.

9. A method of controlling a computer system including a processor, a plurality of devices accessible by said processor via one or more addresses and a bus controller coupled to said processor and said plurality of devices wherein a first device is accessible by said processor via a first subset of addresses in said memory map and a second device is accessible by said processor via a second subset of addresses in said memory map, the method comprising:

configuring a third subset of addresses in said memory map during a first time period by said bus controller such that said processor accesses said first device when said processor seeks to access said third subset of said addresses; and

configuring the third subset of addresses in said memory map during a second time period by said bus controller such that said processor accesses said second device when said processor seeks to access said third subset of said addresses.

10. The method of claim 9 further comprising

controlling which of said devices responds to accesses by said processor based on said memory map via a plurality of device select lines coupled between said bus controller and said plurality of devices.

11. The method of claim 9 further comprising:

selecting the first device from said plurality of devices based on a signal on a select signal line coupled to said bus controller.

12. The method of claim 10 further comprising:

selecting the first device from said plurality of devices based on a signal on a select signal line coupled to said bus controller.

13. A computer system comprising:

a processor;

a plurality of memory devices accessible by said processor via one or more addresses, a second memory device having a faster access speed than a first memory device; and

a bus controller coupled to said processor and said plurality of memory devices, said bus controller adapted to configure a memory map of said addresses for said computer system wherein said first memory device is accessible by said processor via a first subset of addresses in said memory map and said second memory device is accessible by said processor via a second subset of addresses in said memory map, wherein;

when said processor receives a reset command, said bus controller configures a third subset of addresses in said memory map such that said processor accesses said first memory device when said processor seeks to access said third subset of said addresses; and

when said processor receives an interrupt command, said bus controller configures the third subset of addresses in said memory map such that said processor accesses said second memory device when said processor seeks to access said third subset of said addresses.

14. The computer system of claim 13, wherein:

said first memory device is a non-volatile memory device; and

said second memory device is a Random-Access-Memory (RAM) device.