Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons

• US 6,480,978 B1
• Filed: 03/01/1999
• Issued: 11/12/2002
• Est. Priority Date: 03/01/1999
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Roy, Richard S.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Torres, Joseph D.
• Application Number:
  US09/260,459
• Time in Patent Office: 1,352 Days
• Field of Search: 714/718, 714/724, 714/729, 714/735, 714/736, 714/738
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/19107 off-chip wires

Abstract

What is disclosed is a system for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single DUT on the set of tester I/O lines, and circuitry coupled to the set of tester I/O lines to receive the data values from the tester and to provide error values to the tester, the circuitry forwards the data values to each of the plurality of DUTs, the circuitry performs a first comparison of the values of two locations having corresponding addresses in different DUTs after reading from the locations, and in response generates the error values indicative of the first comparison. The circuitry may further perform a second comparison of the values of two different locations in the same DUT to generate further error values indicative of the second comparison.

Claims

1. A system for testing a plurality of integrated circuit devices under test (DUTs), comprising:

a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a DUT on the set of tester I/O lines; and

circuitry coupled to the at least one set of tester I/O lines to receive said data values from the tester and to provide error values to the tester, wherein

the circuitry forwards said data values to each of the plurality of DUTs, and

the circuitry performs a first comparison between the values of two locations having corresponding addresses in different DUTs after reading said locations, and in response generates said error values indicative of the first comparison.

2. The system of claim 1 wherein the circuitry further performs a second comparison between the values of two different locations in the same DUT to generate further error values indicative of the second comparison.

3. The system of claim 1 wherein the DUTs are memory devices and wherein the error values represent an error, if any, in one or more bits of a location in each of the DUTs for a predefined address without specifying a specific bit of the location.

4. The system of claim 1 wherein the circuitry provides a plurality of error bits on said I/O lines, each error bit representing an error, if any, in a separate DUT.

5. The system of claim 1 further comprising:

a probe assembly having a channel for communicating with the tester, the channel being coupled to the set of tester I/O lines, and a plurality of probe elements having one end for contacting a plurality of signal locations of the DUTs and another end connected to the circuitry, the circuitry being a part of the probe assembly and coupled to the channel.

6. A probe assembly comprising:

a channel for communicating with a tester that provides data values for testing a DUT through the channel;

a plurality of probe elements for contacting a plurality of signal locations of one or more devices under test (DUTs); and

tester-DUT interface circuitry coupled between the channel and the probe elements to receive said data values from the tester and to provide error values to the tester, wherein

the circuitry forwards said data values to each of the plurality of DUTs via said probe elements, the circuitry performs a first comparison between the values of two locations having corresponding addresses in different DUTs after reading from said locations, and in response generates error values indicative of the first comparison.

7. The probe assembly of claim 6 wherein the circuitry further performs a second comparison between the values of two different locations in the same DUT to generate further error values indicative of the second comparison.

8. An interface circuit for testing a plurality of DUTs, comprising:

means for receiving a data value and an associated address as part of a test sequence;

means for writing a plurality of copies of said data value at a plurality of corresponding addresses;

means for reading from said plurality of corresponding addresses a plurality of read data values; and

means for performing a first comparison between two of said plurality of read data values to generate an error value representing a difference, if any, between two read data values.

9. The interface circuit of claim 8 further comprising:

means for performing a second comparison between the values of two different locations in the same DUT to generate further error values indicative of the second comparison.

10. An interface circuit for testing a plurality of DUTs, comprising:

channel port for receiving a data value and an associate address as part of a test sequence;

a plurality of DUT ports each for reading data values from and writing data values to a separate DUT; and

first logic coupled to the DUT ports for performing an XOR operation upon two or more corresponding bits of two or more data values read from locations having corresponding addresses in different DUTs.

11. The interface circuit of claim 10 further comprising:

an address mapper coupled to the channel port for generating the corresponding addresses in response to mapping the associated address.

12. The interface circuit of claim 10 further comprising:

second logic coupled to the DUT ports for performing a plurality of second XOR operations corresponding to the plurality of DUTs, each XOR operation being performed between two or more corresponding bits of the same data value read from a location in a separate DUT.

13. The interface circuit of claim 12 further comprising:

logic coupled to the first and second logic for generating an error value in response to performing an OR operation between the results of said first XOR operations and said second XOR operations, the error value indicating errors, if any, in a set of corresponding bits read from each of the DUTs.

14. A method for testing a plurality of DUTs, comprising:

receiving a data value and an associated address as part of a test sequence from a single channel of a tester;

writing a plurality of copies of said data value at a plurality of corresponding addresses in a plurality of DUTs;

reading from said plurality of corresponding addresses in said DUTs a plurality of read data values; and

performing first comparisons between pairs of said plurality of read data values to generate error values representing differences between said pairs of read data values.

15. An integrated circuit test system comprising:

a tester having at least one set of tester input/output (I/O) lines, the tester to use each set to write a data value to a separate device to be tested; and

a contact assembly having two or more sets of elements, each set of elements to contact a plurality of signal locations of a separate device under test (DUT), the contact assembly further includes circuitry having an input coupled to one set of said tester I/O lines and an output coupled to the two or more sets of elements to provide said data value on each set of said elements,

the circuitry being further configured to read from each DUT a read data value in response to receiving a read from the tester over the set of I/O lines, compare a read data value from one DUT to a read data value from another DUT to determine an error in one or both of said DUTs, and send an error value, indicative of the error, to the tester over the set of tester I/O lines.

16. The system of claim 15 wherein the tester is configured to test the separate device as being a memory device.

17. The system of claim 15 wherein the data value is to be carried by one or more data lines of each set and the error value is to be carried by said one or more data lines that were used to carry the write data value.

18. The system of claim 17 wherein each bit of the error value is to be carried on a separate one of said one or more data lines, an error status of each DUT being represented by a separate bit of the error value.

19. The system of claim 17 wherein the contact assembly is further configured to contact each DUT as part of a packaged semiconductor integrated circuit (IC) device.

20. The system of claim 17 wherein the error value is to be carried to the tester by said one or more data lines that were used to carry the write data value.

21. The system of claim 17 wherein the circuitry is to further compare a read data value from a location in one DUT to a read data value from another location in the same DUT to determine a further error in the same DUT, and send a further error value, indicative of the further error, to the tester over the set of tester I/O lines.

22. A contact assembly comprising:

two or more sets of first elements, each set of elements is to contact a plurality of signal locations of a separate device under test (DUT); and

first circuitry having an input to be coupled to one set of I/O lines of a tester and an output coupled to the two or more sets of elements, to provide a write data value, received from the tester over the set of I/O lines, on each set of said elements,

the circuitry being further configured to read from each DUT a read data value, in response to receiving a read from the tester over the set of I/O lines, compare a read data value from one DUT to that from another DUT to determine an error in one or both DUTs, and send an error value, indicative of the error, to the tester over the set of tester I/O lines.

23. The contact assembly of claim 22 wherein the write data value is to be carried by one or more data lines of the set of I/O lines and the error value is to be carried by said one or more data lines that were used to carry the write data value.

24. The contact assembly of claim 23 further comprising:

two or more sets of second elements, each set of second elements to contact a plurality of signal locations of a separate device under test (DUT); and

second circuitry having an input to be coupled to a further set of I/O lines of the tester and an output coupled to the two or more sets of second elements, to provide a write data value, received from the tester and carried by one or more data lines of the further set of I/O lines, on each set of said second elements,

the second circuitry being further configured to read from each DUT that is contacted by the second elements a read data value, in response to receiving a read from the tester over the further set of I/O lines, compare a read data value from one DUT to a read data value from another DUT to determine an error in one or both of the DUTs that are to be contacted by the second elements, and send a second error value, indicative of the error, to the tester over the further set of I/O lines.

25. The contact assembly of claim 24 wherein the first and second circuitry are formed as separate application specific integrated circuits (ASICs).

26. The contact assembly of claim 24 wherein the second error value is to be carried by said one or more data lines in the further set of I/O lines used to carry the write data value.

27. The contact assembly of claim 24 wherein the circuitry is to further compare a read data value from a location in one DUT to a read data value from another location in the same DUT to determine a further error in the same DUT, and send a further error value, indicative of the further error, to the tester over the set of tester I/O lines.

28. An interface circuit for use when coupled between an integrated circuit tester and two or more devices under test (DUTs), comprising:

an input to be coupled to one set of I/O lines of the tester and to receive a write data value from the tester;

an output to be coupled to two or more sets of elements, where each set of elements is to contact a plurality of signal locations of a separate device under test (DUT), to provide said write data value to each set of elements; and

comparison circuitry to compare a data value read from one DUT in response to receiving a read from the tester to a data value read from another DUT to determine an error in one or both DUTs,

wherein the circuitry is to send an error value, indicative of the error, to the tester over the set of tester I/O lines.

29. The interface circuitry of claim 28 wherein the input is to receive the write data value via one or more data lines of the set of I/O lines and the error value is to be carried to the tester by said one or more data lines that were used to carry the write data value.

30. The interface circuitry of claim 29 wherein the circuitry is to further compare a read data value from a location in one DUT to a read data value from another location in the same DUT to determine a further error in the same DUT, and send a further error value, indicative of the further error, to the tester over the set of tester I/O lines.

31. The interface circuitry of claim 29 wherein the read data value and the error value are each no more than M bits long, the data lines of the set of I/O lines are M bits wide, and the comparison circuitry is to provide within the error value information regarding errors in locations of two or more DUTs each of which can store data values up to M bits long.

32. The interface circuitry of claim 29 wherein the error value does not indicate an exact bit location of an error in the DUTs.

33. A method for testing a plurality of devices under test (DUTs), comprising:

receiving via a set of tester I/O lines a write data value from a tester, the tester to use the set to write a data value to a single device to be tested;

providing said write data value to each of two or more sets of elements, where each set of elements is contacting a plurality of signal locations of a separate DUT;

reading a data value from each DUT in response to receiving a read from the tester;

comparing a read data value from one DUT to a read data value from another DUT to determine an error in one or both of said DUTs; and

sending an error value indicative of the error to the tester over the set of tester I/O lines.

34. The method of claim 33 wherein the write data value is received via one or more data lines of the set of tester I/O lines and wherein the error value is being carried by said one or more data lines of the set of I/O lines.

35. The method of claim 34 wherein the read data value and the error value are each no more than M bits long, the data lines of the set of I/O lines are M bits wide, and the error value includes information regarding possible errors in locations of two or more DUTs each of which can store data values that are up to M bits long.

36. The method of claim 34 wherein the error value does not indicate an exact bit location of an error in the DUTs.