Algorithm and methodology for the polygonalization of sparse circuit schematics

• US 6,480,995 B1
• Filed: 04/14/1997
• Issued: 11/12/2002
• Est. Priority Date: 04/15/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Saito, Richard C., Chun, Perry, Chen, Y. Eugene, Schmidt, Dominik J.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US08/840,558
• Time in Patent Office: 2,038 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 716/1, 716/2, 716/8, 716/9, 716/11
• US Class Current: 716/112
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An method of creating a physical layout of an integrated circuit. A schematic file (600) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (600). The method takes advantage of constraints on the schematic design to provide the layout file (675) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.

Claims

1. A method of creating a layout design for an integrated circuit comprising:

providing a first element in a schematic;

providing a second element in said schematic at a position relative to said first element;

providing an interconnection in said schematic between said first and second elements;

creating a first geometry for a layout corresponding to the first element;

creating a second geometry for the layout corresponding to the second element;

placing the second geometry in a position relative to the first geometry so that a positional relationship between the second geometry and the first geometry in the layout is similar to a positional relationship between the second element to the first element in the schematic;

creating a third geometry for the layout corresponding to the interconnection; and

placing the third geometry between the first geometry and the second geometry.

2. The method of claim 1 wherein said first element is an input/output pad of a test chip.

3. The method of claim 1 further comprising moving said second geometry relative to said first geometry to allow said third geometry to couple said first geometry and said second geometry.

4. The method of claim 1 wherein said creating first, second, and third geometry steps and said placing first second, and third geometry steps are executed automatically on a computer system by a software program.

5. The method of claim 1 wherein said software program is stored on a computer-readable medium.

6. A method of creating a layout design for an integrated circuit comprising:

providing a first element in a schematic;

providing a second element in the schematic at a position relative to the first element;

providing an interconnection in the schematic between the first and second elements;

creating a first geometry for a layout corresponding to the first element;

creating a second geometry for the layout corresponding to the second element;

placing the second geometry in a position relative to the first geometry so that a positional relationship between the second geometry and the first geometry in the layout is similar to a positional relationship between the second element to the first element in the schematic;

determining a first path between the first geometry and the second geometry, the first path having substantially the same positional relationship to the first and second geometries as the interconnection has to the first and second elements;

when the first path crosses a fourth geometry, finding a second path from the first geometry to the second geometry, wherein the second path does not cross the third geometry;

creating a third geometry for the layout corresponding to the second path; and

placing the third geometry along the second path.

7. The method of claim 6 wherein said finding a second path step further comprises:

calculating a midpoint between said first and fourth geometries, said midpoint being a point along said first path;

forming a first segment of said second path from said first element to said midpoint;

forming a second segment of said second path from said midpoint, said second segment being perpendicular to said first segment; and

forming a connecting line of said second path from said second segment to said second geometry.

8. The method of claim 7 wherein said first connecting line of said second path includes at least two perpendicular segments.

9. The method of claim 7 further comprising:

calculating a first distance from said first path to a first edge of said fourth geometry;

forming said second segment of said second path with a length greater than said first distance.

10. The method of claim 9 further comprising:

calculating a second distance from said second segment to a second edge of said fourth geometry;

forming a third segment of said second path from said second segment with a length greater than said second distance, said third segment being perpendicular to said second segment.

11. The method of claim 6 wherein said midpoint is a point equidistant from said first geometry and said fourth geometry.

12. A method of designing an integrated circuit comprising:

selecting a plurality of elements to implement a design;

representing said elements as first and second hierarchical symbols, said first and second hierarchical symbol each representing at least one element;

providing a schematic having said first hierarchical symbol at a first location and a second hierarchical symbol at a second location, said first hierarchical symbol not overlapping said second hierarchical symbol;

translating said first hierarchical symbol to a first hierarchical geometry;

translating said second hierarchical symbol to a second hierarchical geometry;

providing a layout having a size proportional to a size of said schematic;

placing said first hierarchical geometry at a third location within said layout, said third location corresponding to said first location in said schematic;

placing said second hierarchical geometries at a fourth location in said layout, said fourth location corresponding to said second location in said schematic;

providing a user-discernible warning if said first hierarchical geometry overlaps said second hierarchical geometry.

13. A computer-implemented method of designing an integrated circuit comprising:

providing a device file containing an element having element parameters;

providing a technology file containing design rules for a particular technology;

forming a first polygon;

using said device file, determining a width of said first polygon;

using said technology file, determining a width of a second polygon;

using said technology file, determining a first spacing, said first spacing being a distance between adjacent second polygons;

using said technology file, determining a second spacing, said second spacing being a distance from an edge of said first polygon to an edge of said second polygon;

calculating a first number of second polygons that may be placed within said first polygon based on said first and second spacing and said width; and

placing said number of second polygons within said first polygon.

14. The method of claim 13 wherein said first number is a maximum number of second polygons that may be placed within said first polygon based on said first and second spacing and said width.

15. The method of claim 14 further comprising:

using said device file, determining a second number of desired second polygons to be placed within said first polygon;

when said second number is greater than said first number, creating an expanded portion of said first polygon; and

placing said second number of second polygons within said expanded portion of said first polygon.

16. The method of claim 14 further comprising:

using said device file, determining a second number of desired second polygons to be placed within said first polygon; and

when said second number is greater than said first number, forming a third polygon adjacent to said first polygon;

placing said second number of second polygons in said first and third polygons.

17. A method of designing an integrated circuit comprising:

providing an element, said element including;

a first polygon, said first polygon being of a first type;

a second polygon, said second polygon being of a second type and within said first polygon;

a third polygon, said third polygon being of a third type; and

a fourth polygon, said fourth polygon being of said second type and within said third polygon;

defining an outline that encloses said element;

calculating a first midpoint for a first edge of said outline;

if said second polygon is not substantially at said midpoint, electrically connecting said second polygon with said first midpoint;

calculating a second midpoint for a second edge of said outline; and

if said fourth polygon is not substantially at said midpoint, electrically connecting said fourth polygon with said second midpoint.

18. The method of claim 17 wherein said first edge and said second edge are opposite edges.

19. The method of claim 17 wherein said first type is said third type.

20. The method of claim 17 wherein said midpoint is a point equidistant between opposite edges of said outline.

21. A method of automatically generating a custom transistor layout, said method comprising the steps of:

specifying a transistor type and an associated set of transistor parameters;

matching said transistor type to a selected cell in a cell library;

identifying physical layout regions for said selected cell;

selectively modifying said physical layout regions in accordance with design library rules; and

drawing said physical layout regions of said selected cell.