Protective layers prior to alternating layer deposition

• US 6,482,733 B2
• Filed: 04/26/2001
• Issued: 11/19/2002
• Est. Priority Date: 05/15/2000
• Status: Expired due to Term

• Current Assignee: ASM International NV
• Original Assignee: ASM Microchemistry Oy (ASM International NV)
• Inventors: Raaijmakers, Ivo, Haukka, Suvi P., Granneman, Ernst H. A., Soininen, Pekka T.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/843,518
• Publication Number:
  US 20010054769A1
• Time in Patent Office: 572 Days
• Field of Search: 438/625, 438/627, 438/632, 438/633, 438/634, 438/637, 438/640, 438/643, 438/681, 438/725
• US Class Current: 438/633
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

Claims

1. A damascene metallization process, comprising:

forming a trench in a desired wiring pattern in a porous insulating layer above a semiconductor substrate;

forming a contact via extending downwardly from a floor of the trench to expose at least part of an underlying conductive element;

blocking pores in an insulating layer sidewall partially defining the trench;

after blocking the pores, lining surfaces of the trench and contact via with no more than about one monolayer by exposure to a first reactant species; and

reacting a second reactant species with the lining monolayer.

2. The method of claim 1, wherein lining comprises supplying a first chemistry excluding the second reactant species and reacting comprises supplying a second chemistry excluding the first reactant species.

3. The method of claim 2, further comprising repeatedly alternating supplying the first chemistry and supplying the second chemistry until a layer forms having a thickness between about 20 Å

and 200 Å

.

4. The method of claim 2, further comprising supplying a carrier gas while repeatedly alternating supplying the first chemistry and supplying the second chemistry.

5. The method of claim 4, wherein the carrier gas purges reactants between supplying the first chemistry and supplying the second chemistry.

6. The method of claim 5, wherein supplying the first chemistry is stopped and the reaction chamber is purged with more than about two chamber volumes of purge gas before supplying the second chemistry.

7. The method of claim 1, wherein lining comprises forming a film in a self-limiting reaction.

8. The method of claim 7, wherein the film formed in the self-limiting reaction is halogen-terminated.

9. The method of claim 8, further comprising removing the halogen termination after lining and prior to reacting the second reactant species.

10. The method of claim 9, wherein removing comprises exposing the halogen termination to a reducing species.

11. The method of claim 10, wherein the reducing species comprises triethyl boron.

12. The method of claim 1, wherein the first reactant species comprises a metal alklyamine.

13. The method of claim 1, wherein the first reactant species is a volatile metal organic compound, and the lining comprises forming a metal-containing film including an organic surface termination.

14. The method of claim 1, wherein the first reactant species comprises a volatile metal halide.

15. The method of claim 1, wherein blocking comprises a non-ALD deposition process.

16. The method of claim 15, wherein blocking comprises a CVD process.

17. The method of claim 15, wherein blocking comprises a PVD process.

18. The method of claim 15, wherein blocking comprises forming a conductive sealing layer.

19. The method of claim 18, wherein blocking comprises penetrating the porous insulating layer with continuous blocking material to no more than about three pore depths.

20. The method of claim 1, wherein the porous insulating layer comprises a spin-on xerogel.

21. The method of claim 1, wherein the porosity of the insulating layer is greater than 50%.

22. The method of claim 1, wherein blocking comprises depositing material at a via bottom by a non-ALD process to a thickness between about 50% and 150% of the average pore size of the insulating layer.

23. The method of claim 1, wherein the insulating layer has a dielectric constant of less than about 2.5.

24. The method of claim 1, wherein blocking comprises alternatingly supplying reactants.

25. The method of claim 24, comprising introducing a first gaseous reactant species into the pores of the insulating layer sidewall, stopping flow of the first reactant and subsequently introducing a second gaseous reactant into the pores.

26. The method of claim 25, wherein the second reactant species that reacts with residual amounts of the first gaseous reactant species within the pores of the insulating layer.

27. The method of claim 26, wherein blocking comprises depositing a conductive material to seal the pores of the insulating layer.

28. The method of claim 24, wherein blocking comprises forming a conductive sealing layer.