Solid state optical shutter

• US 6,483,094 B1
• Filed: 01/03/2000
• Issued: 11/19/2002
• Est. Priority Date: 04/08/1997
• Status: Expired due to Term

• Current Assignee: Microsoft International Holdings BV (Microsoft Corporation)
• Original Assignee: 3DV Systems Ltd. (Microsoft Corporation)
• Inventors: Iddan, Gavriel J., Yahav, Giora
• Primary Examiner(s): ALLEN, STEPHONE B
• Application Number:
  US09/402,854
• Time in Patent Office: 1,051 Days
• Field of Search: 250/214.1, 250/214.LS, 250/214.R, 250/237.R, 250/216, 327/514, 327/515, 310/303
• US Class Current: 250/214.00R
• CPC Class Codes: H01L 31/143 the light source being a semiconductor device with at least one potential-jump barrier or surface barrier, e.g. light emitting diode

Abstract

A solid-state optoelectronic shutter having an input and an output, comprising a semiconductor material, having formed therein or thereon: a planar photodiode (24), having a planar surface, and optically communicating with the input; a planar LED layer (26), having a planar surface substantially parallel to the planar photodiode, and optionally communicating with the output; and a planar gate layer (28), intermediate the planar photodiode and the planar LED.

Claims

1. A solid-state optoelectronic shutter having an input face and an output face, comprising a semiconductor material, having formed therein or thereon:

a planar photodiode, having a planar surface, and optically communicating with the input face;

a planar LED layer, having a planar surface substantially parallel to the planar photodiode, and optically communicating with the output face;

a planar gate layer, intermediate the planar photodiode and the planar LED which gates the flow of charge carriers between the photodiode and the LED; and

first and second transparent, conductive coatings on the input and output faces, respectively,

a control voltage source which applies a control voltage is applied between the first and second coatings to switch or modulate light generated at the output face.

2. A shutter according to claim 1, when the semiconductor material comprises substantially a single crystal, and wherein an axis of the crystal is oriented in a direction substantially perpendicular to the planar surfaces of the photodiode and the LED.

3. A shutter according to claim 1, wherein the semiconductor material comprises a material selected from the group consisting of silicon, GaAs and InP.

4. A shutter according to claim 1, wherein the photodiode has a planar PIN structure.

5. A shutter according to claim 1, wherein the photodiode comprises a planar avalanche photodiode.

6. A shutter according to claim 5, and comprising a transparent, conductive layer between the photodiode and the gate layer, wherein an electrical potential is applied to the conductive layer to reverse-bias the photodiode.

7. A shutter according to claim 1, wherein the control voltage is applied across the gate layer so as to permit electrons to flow therethrough, from the photodiode to the LED, thereby opening the shutter.

8. A shutter according to claim 1, wherein the semiconductor material is comprised in a generally planar substrate having input and output faces.

9. A shutter according to claim 8, and comprising metal coatings on peripheral portions of the input and output faces, wherein the metal coatings are electrically coupled to the transparent, conductive coatings for application of the control voltage therethrough.

10. A shutter according to claim 1 wherein the planar photodiode is proximate the input face.

11. A shutter according to claim 1 wherein the planar LED is proximate the output face.

12. A shutter according to claim 1 wherein the planar photodiode, the gate layer and the planar LED are formed proximate one of the input and output faces.

13. A shutter according to claim 12 wherein the semiconductor material is formed as a planar substrate that is thinned between the formed planar devices and the other face.

14. A shutter according to claim 1 wherein the semiconductor material is formed as a planar substrate and at least one of the faces is a face of semiconductor material epitaxially grown on the substrate and wherein at least one of the planar photodiode and the planar LED is formed in the epitaxially grown material.

15. A method for producing an integrated imaging device, comprising providing an optoelectronic shutter according to claim 1 and optically coupling the shutter to a front surface of an optical detector array.

16. A method according to claim 15 wherein optically coupling comprises fixing the shutter with respect to the front surface of the array.

17. A method according to claim 16, wherein fixing the shutter comprises cementing the shutter to the surface.

18. A method according to claim 16, wherein fixing the shutter to the front surface of the detector array comprises cementing a first side of a faceplate to the surface and cementing the shutter to a second side of the faceplate, opposite the first side and optically communicating therewith.

39. An integrated image detection device, comprising:

an optical detector array, having a front surface; and

a shutter according to claim 1, optically coupled to the front surface of the array so as to modulate light incident on the array through the shutter.

40. A device according to claim 39 wherein the output surface of the shutter is fixed with respect to the front surface of the array.

41. A device according to claim 39, wherein the output surface of the shutter is directly attached to the front surface of the array.

42. A device according to claim 39, ad comprising a faceplate, which conveys an optical image between first and second sides thereof, wherein the first side of the faceplate is attached to the output face of the shutter, and the second side of the faceplate is attached to the front surface of the array.

19. An optical shutter comprising:

a photodiode which receives light an produces charge carriers;

a LED which receives the charge carriers and produces light responsive to the carriers;

a gate which gates the flow of carriers from the photodiode to the LED; and

a transparent, conductive layer between the photodiode and the gate;

wherein said photodiode, LED, gate and conductive layer form a monolithic structure.

20. An optical shutter according to claim 19 and including a semiconductor filled region, situated intermediate the photodiode and the LED, through which the charge carriers flow.

21. A shutter according to claim 20 wherein the semiconductor material comprises a material selected from the group consisting of silicon, GaAs and InP.

22. A shutter according to claim 19, wherein the photodiode has a PIN structure.

23. A shutter according to claim 19, wherein the photodiode comprises an avalanche photodiode.

24. A shutter according to claim 19 wherein an electrical potential is applied to the conductive layer to reverse-bias the photodiode.

25. A shutter according to claim 19, wherein a control voltage is applied across the gate layer so as to permit electrons to flow therethrough, from the photodiode to the LED, thereby opening the shutter.

26. An integrated image detection device, comprising:

an optical detector array, having a front surface; and

a shutter according to claim 19, optically coupled to the front surface of the array so as to modulate light incident on the array through the shutter.

27. A method for producing an integrated imaging device, comprising providing an optoelectronic shutter according to claim 19 and optically coupling the shutter to a front surface of an optical detector array.

28. A method for producing an optoelectronic device, comprising:

providing a generally planar substrate made of semiconductor material, having input and output faces;

producing a planar photodiode proximate the input face, external to the gate layer;

producing a LED proximate the output face, external to the gate layer;

producing a gate layer within the substrate between the input and output faces, which gate layer gates the flow of carriers between the photodiode and the LED; and

depositing transparent, conductive coatings on the input and output faces.

29. A method according to claim 28 and comprising depositing metal coatings on peripheral portions of the input and output faces, in electrical contact with the transparent, conductive coatings thereon.

30. A method according to claim 29, and comprising attaching electrical leads to the metal coatings, for applying a control voltage thereto.

31. A method according to claim 28, wherein producing the gate layer comprises implanting ions in the substrate.

32. A method according to claim 28, wherein producing the photodiode comprises doping the substrate to form a planar PIN structure therein.

33. A method according to claim 28, wherein producing the photodiode comprises forming an avalanche photodiode structure at the input face of the substrate.

34. A method according to claim 33, and comprising producing a conductive layer intermediate the gate layer and the photodiode for applying a biasing voltage to the photodiode.

35. A method according to claim 28 wherein the photodiode is formed proximate the input face.

36. A method according to claim 28 wherein the photodiode is formed proximate the output face.

37. A method according to claim 28 wherein the photodiode, the gate layer and the LED are formed proximate one of the input and output faces.

38. A method according to claim 37 and including thinning the substrate between the formed photodiode, gate layer and LED and the other of the input and output faces.

43. An integrated image detection device, comprising:

an optical detector array, having a front surface; and

a solid state optoelectronic shutter having an input face and an output face, comprising a semiconductor material, having formed thereon or therein;

a planar photodiode, having a planar surface, and optically communicating with the input face;

a planar LED layer, having a planar surface substantially parallel to the planar photodiode, and optically communicating with the output face; and

a planar gate layer, intermediate the planar photodiode and the planar LED which gate layer controls carrier flow between the photodiode and the LED;

said shutter being optically coupled to the front surface of the array so as to modulate light incident on the array through the shutter.

44. An integrated image detection device, comprising:

a monolithic solid state optical shutter having an input face and an output face, comprising a semiconductor material, having formed thereon or therein;

a photodiode which receives light and produces charge carriers;

a LED which receives the charge carriers and produces light responsive to the carriers; and

a gate which gates the flow of carriers from the photodiode to the LED; and

an optical detector array, having a front surface which receives light from the LED.

45. A method for producing an integrated imaging device, comprising:

providing an optoelectronic shutter having an input face and an output face; and

optically coupling the shutter to a front surface of an optical detector array, said shutter comprising;

a planar photodiode, having a planar surface, and optically communicating with the input face;

a planar LED layer, having a planar surface substantially parallel to the planar photodiode, and optically communicating with the output face; and

a planar gate layer, intermediate the planar photodiode and the planar LED which modulates or switches a flow of carriers from the photodiode to the LED.

46. A method for producing an integrated imaging device, comprising:

providing an optoelectronic shutter having an input face and an output face; and

optically coupling the shutter with respect to a front surface of an optical detector array, said shutter comprising;

a photodiode which receives light and produces charge carriers;

a LED which receives the charge carriers and produces light responsive to the carriers; and

a gate which gates the flow of carriers from the photodiode to the LED to modulate or switch the light output of the LED.