Semiconductor memory device formed on semiconductor substrate

• US 6,483,139 B1
• Filed: 10/23/2001
• Issued: 11/19/2002
• Est. Priority Date: 07/05/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Arimoto, Kazutami, Shimano, Hiroki
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US09/983,294
• Time in Patent Office: 392 Days
• Field of Search: 257/296, 257/301, 257/300, 257/306, 257/308, 257/379, 257/295, 257/550, 257/903, 257/904, 257/71, 257/303, 257/304, 257/311, 257/327, 257/329, 257/330-332, 257/334, 257/297, 438/253, 438/396, 438/256, 438/399, 365/63, 365/230.03, 365/51, 365/190, 365/149
• US Class Current: 257/296
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.

Claims

1. A semiconductor memory device formed on a semiconductor substrate, comprising:

a memory cell having an MOS transistor and a capacitor connected in series for storing a data signal, wherein

said MOS transistor includes a gate insulating film formed on a surface of said semiconductor substrate, a gate electrode formed on a surface of the gate insulating film, and an impurity diffusion region formed on the surface of said semiconductor substrate on either side of the gate electrode,

said capacitor includes an impurity diffusion region formed on the surface of said semiconductor substrate, an insulating film formed on a surface of the impurity diffusion region, and a plate electrode formed on a surface of the insulating film for receiving a reference potential, and

the gate electrode of said MOS transistor and the plate electrode of said capacitor are formed by a same interconnection layer.

2. The semiconductor memory device according to claim 1, wherein

said semiconductor memory device is formed on said semiconductor substrate together with a logic circuit including an MOS transistor, and

a gate electrode of the MOS transistor of said logic circuit, the gate electrode of the MOS transistor of said memory cell, and the plate electrode of said capacitor are formed by the same interconnection layer.

3. The semiconductor memory device according to claim 1, wherein

the MOS transistor of said memory cell is an N-channel MOS transistor, said semiconductor memory device further comprising:

a word line connected to a gate of said N-channel MOS transistor;

first and second bit lines, one of which is connected to a source of said N-channel MOS transistor;

a first P-channel MOS transistor connected between said first bit line and a first node;

a second P-channel MOS transistor connected between said second bit line and a second node; and

a write circuit for writing a data signal into said memory cell, wherein

said write circuit performs the steps of;

supplying a ground potential to gates of said first and second P-channel MOS transistors to render said first and second P-channel MOS transistors conductive;

supplying a boosted potential that is higher than a power-supply potential to said word line to render the N-channel MOS transistor of said memory cell conductive;

causing one of said first and second nodes to attain said power-supply potential while causing other node to attain said ground potential according to an externally supplied write data signal; and

supplying a negative potential that is lower than said ground potential to gates of said first and second P-channel MOS transistors while supplying said power-supply potential to said word line.

4. The semiconductor memory device according to claim 3, wherein

an absolute value of a threshold voltage of each of said first and second P-channel MOS transistors is set to be substantially equal to a voltage of a difference between said boosted potential and said power-supply potential.

5. The semiconductor memory device according to claim 3, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

two word lines are provided,

gates of N-channel MOS transistors of said two memory cells are respectively connected to said two word lines, and

sources of the N-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

6. The semiconductor memory device according to claim 3, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

gates of N-channel MOS transistors of said two memory cells are both connected to said word line, and

sources of the N-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

7. The semiconductor memory device according to claim 1, wherein

the MOS transistor of said memory cell is a P-channel MOS transistor, said semiconductor memory device further comprising:

a word line connected to a gate of said P-channel MOS transistor;

first and second bit lines, one of which is connected to a source of said P-channel MOS transistor;

a first N-channel MOS transistor connected between said first bit line and a first node;

a second N-channel MOS transistor connected between said second bit line and a second node; and

a write circuit for writing a data signal into said memory cell, wherein

said write circuit performs the steps of;

supplying a power-supply potential to gates of said first and second N-channel MOS transistors to render said first and second N-channel MOS transistors conductive;

supplying a negative potential that is lower than a ground potential to said word line to render the P-channel MOS transistor of said memory cell conductive;

causing one of said first and second nodes to attain said power-supply potential while causing other node to attain said ground potential according to an externally supplied write data signal; and

supplying a boosted potential that is higher than said power-supply potential to gates of said first and second N-channel MOS transistors while supplying said ground potential to said word line.

8. The semiconductor memory device according to claim 7, wherein

a threshold voltage of said first and second N-channel MOS transistors is set to be substantially equal to a voltage of a difference between said ground potential and said negative potential.

9. The semiconductor memory device according to claim 7, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

two word lines are provided,

gates of P-channel MOS transistors of said two memory cells are respectively connected to said two word lines, and

sources of the P-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

10. The semiconductor memory device according to claim 7, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

gates of P-channel MOS transistors of said two memory cells are both connected to said word line, and

sources of the P-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

11. The semiconductor memory device according to claim 1, wherein

the MOS transistor of said memory cell is an N-channel MOS transistor, said semiconductor memory device further comprising:

a word line connected to a gate of said N-channel MOS transistor;

first and second bit lines, one of which is connected to a source of said N-channel MOS transistor; and

a write circuit for writing a data signal into said memory cell, wherein

said write circuit performs the steps of;

supplying a boosted potential that is higher than a power-supply potential to said word line to render the N-channel MOS transistor of said memory cell conductive;

supplying said power-supply potential to said first and second bit lines;

supplying said power-supply potential to said word line; and

causing one of said first and second bit lines to attain said power-supply potential while causing other bit line to attain a ground potential according to an externally supplied write data signal.

12. The semiconductor memory device according to claim 11, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

two word lines are provided,

gates of N-channel MOS transistors of said two memory cells are respectively connected to said two word lines, and

sources of the N-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

13. The semiconductor memory device according to claim 11, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

gates of N-channel MOS transistors of said two memory cells are both connected to said word line, and

sources of the N-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

14. The semiconductor memory device according to claim 1, wherein

the MOS transistor of said memory cell is a P-channel MOS transistor, said semiconductor memory device further comprising:

a word line connected to a gate of said P-channel MOS transistor;

first and second bit lines, one of which is connected to a source of said P-channel MOS transistor; and

a write circuit for writing a data signal into said memory cell, wherein

said write circuit performs the steps of;

supplying a negative potential that is lower than a ground potential to said word line to render the N-channel MOS transistor of said memory cell conductive;

supplying said ground potential to said first and second bit lines;

supplying said ground potential to said word line; and

causing one of said first and second bit lines to attain a power-supply potential while causing other bit line to attain said ground potential according to an externally supplied write data signal.

15. The semiconductor memory device according to claim 14, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

two word lines are provided,

gates of P-channel MOS transistors of said two memory cells are respectively connected to said two word lines, and

sources of the P-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

16. The semiconductor memory device according to claim 14, wherein

two memory cells are provided, and one data signal is stored using said two memory cells,

gates of P-channel MOS transistors of said two memory cells are both connected to said word line, and

sources of the P-channel MOS transistors of said two memory cells are respectively connected to said first and second bit lines.

17. The semiconductor memory device according to claim 1, wherein

two memory cells are provided, and one data signal is stored using said two memory cells, and

an MOS transistor of one of said two memory cells is an N-channel MOS transistor, and an MOS transistor of other memory cell is a P-channel MOS transistor, said semiconductor memory device further comprising:

first and second word lines respectively connected to a gate of said N-channel MOS transistor and a gate of said P-channel MOS transistor;

first and second bit lines, one of which is connected to a source of said N-channel MOS transistor and a source of said P-channel MOS transistor; and

a write circuit for writing a data signal into said two memory cells, wherein

said write circuit performs the steps of;

supplying a power-supply potential and a ground potential respectively to said first and second word lines to render conductive said N-channel MOS transistor and said P-channel MOS transistor; and

causing one of said first and second bit lines to attain said power-supply potential while causing other bit line to attain said ground potential according to an externally supplied write data signal.