Configurable computational unit embedded in a programmable device

• US 6,483,343 B1
• Filed: 12/29/2000
• Issued: 11/19/2002
• Est. Priority Date: 12/29/2000
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Lai, Gary N., Oelsner, Thomas, Faith, Brian C.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/751,538
• Time in Patent Office: 690 Days
• Field of Search: 326/37-41, 708/625, 708/523, 708/632
• US Class Current: 326/40
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

A plurality of configurable computational units are embedded in a programmable device, such as a field programmable gate array. Each configurable computational unit includes an adder circuit that is switchably coupled to a multiplier circuit and an accumulator circuit. The configurable computational unit may be configured permanently or on-the-fly to perform desired arithmetic type functions efficiently and effectively. For example, the computational unit may be configured for digital signal processing functions, filtering functions, and algorithm functions. The computational units may be cascaded by programmably connecting the computational units together, e.g., through the routing resources of the programmable device.

Claims

1. A programmable logic device, comprising:

a plurality of input/output cells;

an array of macrocells;

a plurality of routing resources that programmably couple said macrocells and said input/output cells; and

at least one configurable computational unit programmably coupled to said routing resources, said configurable computational unit comprising at least an adder circuit and a multiply circuit.

2. The programmable logic device of claim 1, wherein said configurable computational unit further comprises an accumulate circuit.

8. The programmable logic device of claim 1, wherein said configurable computational unit having a plurality of instruction terminals that are programmably coupled to said routing resources, said instruction terminals receiving signals for configuring said configurable computational unit.

9. The programmable logic device of claim 1, wherein said configurable computational unit spans the length of at least four logic cells.

11. The programmable logic device of claim 1, comprising a plurality of configurable computational units, wherein said plurality of configurable computational units are programmably coupled together through said routing resources.

3. A programmable logic device, comprising:

a plurality of input/output cells;

an array of macrocells;

a plurality of routing resources that programmably couple said macrocells and said input/output cells; and

at least one configurable computational unit programmably coupled to said routing resources, said configurable computational unit comprising;

at least an adder circuit and a multiply circuit; and

said adder circuit switchably coupled to said multiply circuit and an accumulate circuit.

4. The programmable logic device of claim 3, wherein said multiply circuit is switchably coupled to said accumulate circuit.

5. The programmable logic device of claim 3, said configurable computational unit further comprising:

a first input terminal coupled to said multiply circuit and switchably coupled to said adder circuit;

a second input terminal switchably coupled to said adder circuit;

said accumulate circuit comprises a register switchably coupled to said adder circuit; and

an output terminal switchably coupled to said multiply circuit, said adder circuit and said register.

6. The programmable logic device of claim 5, wherein said multiply circuit comprises a multiplicand terminal and a multiplier terminal, said first input terminal of said configurable computational unit is coupled to said multiplicand terminal and said multiplier terminal.

7. The programmable logic device of claim 6, wherein said first input terminal of said configurable computational unit is split to provide said multiplicand terminal with m bits and said multiplier terminal with n bits.

10. The programmable logic device of claim 3, wherein said configurable computational unit further comprises a register coupled to said adder circuit and an output terminal that is switchably coupled to said multiply circuit, said adder circuit, and said register.

12. An apparatus comprising:

a field programmable gate array;

a plurality of configurable computational units embedded within said field programmable gate array, each of said configurable computational units having an adder circuit switchably coupled to an m×

n multiply circuit and an accumulator circuit.

13. The apparatus of claim 12, wherein each of said configurable computational units further comprises an output terminal switchably coupled to said m×

n multiply circuit, said adder circuit and said accumulator circuit.

16. The apparatus of claim 12, wherein said field programmable gate array comprises a of input/output cells, an array of macrocells, and a plurality of routing resources, each of said configurable computational units further comprising instruction terminals programmable coupled to macrocells and said input/output cells, said instruction terminals receiving signals indicating the desired configuration of said configurable computational unit.

17. The apparatus of claim 12, wherein the plurality of configurable computational units are programmably coupled together.

18. The apparatus of claim 12, further comprising a means for permanently configuring a configurable computational unit to perform a desired function and a means for temporarily configuring said configurable computation unit to perform a desired function.

14. An apparatus comprising:

a field programmable gate array;

a plurality of configurable computational units embedded within said field programmable gate array, each of said configurable computational units comprises;

an adder circuit switchably coupled to an m×

n multiply circuit and an accumulator circuit;

a first input terminal for receiving a first set of data;

said m×

n multiply circuit having a multiplicand terminal coupled to said first input terminal, a multiplier terminal coupled to said first input terminal, and an output terminal, said multiplicand receiving m bits of data from said first set of data and said multiplier terminal receiving n bits of data from said first set of data;

a first multiplexer circuit having a first data terminal coupled to said output terminal of said m×

n multiply circuit, a second data terminal coupled to said first input terminal, an output terminal, and a select terminal; and

said adder circuit having a first input terminal coupled to said output terminal of said first multiplexer circuit, and having a second input terminal and an output terminal.

15. The apparatus of claim 14, wherein each of said configurable computational units further comprises:

a second input terminal for receiving a second set of data;

a second multiplexer circuit having a first data terminal coupled to said second input terminal, a second data terminal, an output terminal coupled to said second input terminal of said adder circuit, and a select terminal;

a register having an input terminal coupled to said output terminal of said adder circuit, said register having an output terminal coupled to said second data terminal of said second multiplexer circuit; and

a third multiplexer having a first data terminal coupled to said output terminal of said m×

n multiply circuit, a second data terminal coupled to said output terminal of said adder circuit, a third data terminal coupled to said output terminal of said register, a pair of select terminals, and an output terminal.

19. A programmable logic device, comprising:

a plurality of input/output cells;

an array of macrocells;

a plurality of routing resources that programmably couple said macrocells and said input/output cells; and

a plurality of configurable computational units embedded within said programmable logic device and programmably coupled to said routing resources, wherein said configurable computational units are restricted from use when said programmable logic device is a virtual device.

20. The programmable logic device of claim 19, wherein said configurable computational unit comprises an adder circuit switchably coupled to a multiply circuit and an accumulate circuit.

21. The programmable logic device of claim 20, wherein said multiply circuit is switchably coupled to said accumulate circuit.