Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 6,483,736 B2
• Filed: 08/24/2001
• Issued: 11/19/2002
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek, Lee, Thomas H., Farmwald, Paul Michael, Johnson, Mark G.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/939,431
• Publication Number:
  US 20020027793A1
• Time in Patent Office: 452 Days
• Field of Search: 365/103, 365/164, 365/114, 365/120, 365/130
• US Class Current: 365/130
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A 3-dimensional memory array built above a substrate, the memory array comprising:

N layers of memory cells;

N+1 layers of conductors;

said memory cells and conductors fabricated using no more than N+1 masks.

2. A memory comprising:

the memory array of claim 1; and

at least one contact which electrically couples said conductors to the substrate.

3. The memory array of claim 1 wherein each memory cell comprises a state change element and a steering element.

4. The memory array of claim 1 wherein the layers of conductors are disposed between memory cell layers and are arranged such that a vertical projection of a first conductor in a first layer of conductors intersects a second conductor in a second layer of conductors.

5. The memory array of claim 4 wherein the conductors run in substantially orthogonal directions between sequential layers of memory cells.

6. The memory of claim 2 wherein the substrate comprises monocrystalline silicon.

7. The memory array of claims 1, 3, 4 or 5 wherein the substrate comprises monocrystalline silicon.

8. The memory of claim 1 wherein each level of conductors is shared between 2 layers of memory cells.

9. The memory of claim 8 wherein the substrate comprises monocrystalline silicon.

10. The memory of claim 9 wherein at least some conductors are self-aligned with at least some memory cells.

18. The memory array of claim 1 wherein each memory cell comprises a state change element and a steering element.

11. A 3-dimensional memory built above a substrate, the memory comprising:

N layers of memory cells;

N+1 layers of conductors;

at least one contact connecting each of the layers of conductors to the substrate;

said memory cells, conductors and contacts being fabricated with no more than 2N+1 masks.

12. The memory of claim 11 wherein the memory is fabricated with no more than N+2 masks.

13. The memory of claims 11 or 12 wherein the substrate comprises monocrystalline silicon.

14. The memory of claims 11 or 12 wherein at least some conductors are self-aligned with at least some memory cells.

15. The memory of claims 11 or 12 wherein at least some conductors are shared between successive layers of memory cells.

16. The memory array of claim 11 or 12 wherein the conductors are disposed between memory cell layers and are arranged such that a vertical projection of a first conductor intersects a second conductor.

17. The memory array of claim 11 or 12 wherein between sequential layers of memory cells the conductors run in substantially orthogonal directions.

19. A 3-dimensional memory built above a monocrystalline substrate, the memory comprising:

N layers of memory cells, each memory cell comprising a state change element and a steering element;

N+1 layers of conductors shared between successive memory cell layers and

arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer;

at least one contact connecting each conductor to the substrate;

said memory cells, conductors and contacts being fabricated with no more than 2N+1masks.

20. A 3-dimensional memory built above a monocrystalline substrate, the memory comprising:

N layers of memory cells, each memory cell comprising a state change element and a steering element;

N+1 layers of conductors shared between successive memory cell layers and arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer, and a memory cell is formed between said first and second conductors at the projection;

at least one contact connecting each conductor to the substrate;

said memory cells, conductors and contacts being fabricated with no more than N+2 masks.