Dynamic DRAM refresh rate adjustment based on cell leakage monitoring

• US 6,483,764 B2
• Filed: 01/16/2001
• Issued: 11/19/2002
• Est. Priority Date: 01/16/2001
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chen Hsu, Louis Lu, Frankowsky, Gerd, Weinfurtner, Oliver
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/761,045
• Publication Number:
  US 20020136075A1
• Time in Patent Office: 672 Days
• Field of Search: 365/222, 365/203, 365/230.03, 365/189.02, 365/189.07, 365/189.08
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/2254 Calibration

Abstract

A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.

Claims

1. A method of adjusting a dynamic DRAM refresh rate based on cell leakage monitoring, comprising:

fabricating the DRAM with a multitude of integrated memory cells;

directly measuring the leakage rate of at least one of the integrated memory cells; and

adjusting a cell ref rate based on the measured leakage rate;

wherein the fabricating step includes the steps of

i) providing said at least one of the memory cells with a first, charging gate to charge said one cell, and

ii) providing said at least one of the memory cells with a second gate for evaluating the charge stored in said one cell; and

the directly measuring step includes the step of evaluating said one of the cells, through the second gate

to identify a voltage level for said at least one of the cells.

2. A method according to claim 1 wherein:

the evaluating step includes the step of evaluating said one of the cells, through the second gate, to apply the voltage level of said at least one of the cells to a series of voltage comparators to identify a voltage level for said at least one of the cells.

3. A method according to claim 2, wherein said at least one of the memory cells is a monitor cell or monitor cell group.

4. A method according to claim 2, wherein the adjusting step includes the step of adjusting the cell refresh rate based on the identified cell voltage level.

5. A dynamic random access memory (DRAM), comprising:

an array of memory cells integrally formed in the DRAM;

a cell leakage monitoring circuit integrally formed in the DRAM to directly measure the leakage rate of at least one of the cells of the DRAM; and

a refresh rate adjustment circuit to adjust a cell refresh rate based on the measured leakage rate; and

wherein said at least one of the cells includes a first, charging gate to charge said one cell, and a second gate for evaluating the charge stored in said at least one cell.

6. A dynamic random access memory according to claim 5, wherein:

i) the cell leakage monitoring circuit includes

ii) a series of voltage comparators, and

a subcircuit to apply the voltage level of said one of the cells to the series of voltage comparators to identify a voltage level for said at least one of the cell.

7. A dynamic random access memory according to claim 6, wherein the adjustment circuit adjusts the cell refresh rate based on the identified voltage level.

8. A method for refreshing the cells of a DRAM, comprising:

issuing a refresh command to pre-charge a monitor cell and to activate a self-refresh circuit;

the self-refresh circuit starting a refresh operation from a first word-line address to a last word-line address;

after refreshing the last word-line address, evaluating the monitor cell;

after evaluating the monitor cell, recharging the monitor cell;

using the result of the evaluation to adjust the refresh cycle time through a control circuit; and

using the adjusted refresh cycle time in the next refresh cycle from the first word-line to the last word-line;

wherein the step of using the result of the evaluation to adjust the refresh cycle time includes the steps of;

generating a first set and a set of signals based on the evaluation of the monitor cell using the first set of signals to make a coarse adjustment of the refresh cycle time; and

using the second set of signals to make a fine adjustment of the refresh cycle time.

9. A method according to claim 8 wherein:

the step of using the first set of signals includes the stop of applying the first set of signals to set a counter; and

the step of using the second set of signals includes the step of applying the second set of signals to adjust the frequency of a base clock generator.

10. A method according to claim 8, wherein the DRAM is a stand alone DRAM chip.

11. A method according to claim 8, wherein the DRAM has a multi-bank architecture.

12. A method according to claim 8, wherein the DRAM is an embedded DRAM cache.

13. A method according to claim 8, wherein the DRAM includes several DRAM chips installed in a module.