Communication system for driving pairs of twisted pair links

• US 6,483,802 B1
• Filed: 05/11/2000
• Issued: 11/19/2002
• Est. Priority Date: 07/11/1996
• Status: Expired due to Term

• Current Assignee: 4Links Limited
• Original Assignee: 4Links Limited
• Inventors: Walker, Christopher Paul Hulme, Cook, Barry Michael
• Primary Examiner(s): Ton, Dang
• Assistant Examiner(s): NGUYEN, BRIAN D
• Application Number:
  US09/569,498
• Time in Patent Office: 922 Days
• Field of Search: 370/200, 370/419, 370/439, 370/357, 370/366, 370/367, 370/368, 370/513, 370/514, 375/293, 375/257, 375/258
• US Class Current: 370/200
• CPC Class Codes: H03M 5/16 the pulses having three levels
• CPC Class Codes: H04B 3/02 Details
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

A communication. system includes two high speed communication links formed by pairs of transformers at either end thereof. A phantom circuit formed by the pairs of transformers is used to distribute power to devices connected to the high speed links. In transmission part of a communications system, data is transmitted under the control of a continuously variable frequency clock. Transmission is on parallel data-strobe links, and the receive includes circuitry to identify on which parallel the data signal is preset. A method and circuitry is provided for transmitting and receiving dc balanced data strobe signals.

Claims

1. A method of encoding data and strobe signals for transmission between first and second interconnected devices, the method including the steps of:

establishing a data signal path between said interconnected devices;

establishing a parallel strobe signal path between said interconnected devices,

generating at said first device a binary data signal for transmission from said first device to said second device on said data signal path, said binary data signal carrying data comprising signal level transitions at predetermined bit boundaries;

generating a binary strobe signal for transmission from said first device to said second device on said strobe signal path, said binary strobe signal carrying timing information comprising signal level transitions at bit boundaries, said binary strobe signal having signal transitions at bit boundaries other than said predetermined bit boundaries on the parallel binary data signal;

encoding said binary data signal into a ternary data signal and said binary strobe signal into a ternary strobe signal, wherein the encoding step comprises selective inversion of signal levels such that each of said ternary signals is DC balanced for transmission from said first device to said second device.

2. The method of claim 1, wherein the encoding step comprises the steps of, for each of the data and strobe signal:

calculating a running digital sum of the ternary signal;

transmitting a next binary 1 as ternary −

1 if a running digital sum is positive and at least two 0'"'"'s have been transmitted since a last ternary +1;

transmitting a next binary 1 as ternary +1 if the running digital sum is negative and at least two 0'"'"'s have been transmitted since a last ternary −

1;

transmitting at least two successive binary 1'"'"'s as ternary −

1'"'"'s if the running digital sum is positive and at least two binary 1'"'"'s follow any number of 0'"'"'s;

transmitting at least two successive binary 1'"'"'s as ternary +1'"'"'s if the running digital sum is negative and the at least two binary 1'"'"'s follow any number of 0'"'"'s; and

otherwise reversing a respective polarity of each ternary 1 each time a run of at least one 0 occurs.

3. The method of claim 1, wherein the step of generating the binary data signal comprises:

receiving n binary bits for transmittal;

adding a flag bit to the n binary bits to form an n+1 bit binary code-word;

calculating a running digital sum of successively formed binary code-words;

outputting as the binary data signal successive code-words in which the n binary bits are in an inverted or non-inverted state depending on a current running digital sum oft he binary code-words, a flag bit being set to indicate inverted data.

4. The method of claim 3, wherein code-words having non-zero disparity are one of inverted and un-inverted such that a magnitude of the running digital sum at code-word boundaries is reduced.

5. The method of claim 3, wherein said adding step includes adding a parity bit to form a n+2 bit code-word.

6. The method of claim 5, wherein a value of the parity bit is selected to ensure an odd number of 1'"'"'s in the code-word.

7. The method of claim 5, wherein binary code-words having zero disparity are not inverted.

8. The method of claim 5, wherein for code-words having zero disparity, code-words containing inverse data with a set flag bit are reserved for control purposes.

9. The method of claim 5 wherein for those code-words having zero disparity, the code-words containing the inverse data thereof with the flag bit set are used to substitute code-words to limit the running digital sum at boundaries of the binary code-words.

10. The method of claim 5, wherein for code-words having zero disparity, code-words containing inverse data thereof with a set flag bit are used to substitute code-words to minimize a run length on the ternary data and strobe signals.

11. The method of claims 3, wherein n=8.

12. The method of claim 1, wherein no data is available for transmission, the encoding step comprises generating extra ternary signals on each ofthe data and strobe signal communication paths until a running digital sum on each of said paths becomes zero, and then ceasing to generate further. ternary signals on said paths.

13. Data transmission circuitry for encoding data and strobe signals for transmission between first and second interconnected devices, comprising:

input circuitry adapted to receive a binary data signal and to supply said binary data signal for transmission on a data signal path between said interconnected devices, said binary data signal carrying data comprising signal level transitions at predetermined bit boundaries;

strobe-generation circuitry adapted to generate a parallel binary strobe signal for transmission on a strobe signal path between said interconnected devices, said binary strobe signal having signal transitions at bit boundaries other than said predetermined bit boundaries on the parallel binary data signal;

encoding circuitry adapted to encode said binary data signal into a ternary data signal and said binary strobe signal into a ternary strobe signal, wherein the encoding circuitry comprises an inverter arranged to selectively invert signal levels such that each of said ternary signals is DC balanced; and

output circuitry for transmitting the ternary encoded data and strobe signals.

14. Data transmission circuitry according to claim 13, further comprising calculation circuitry for calculating a disparity of code-words, wherein when the disparity of a code-word is zero data therein is not inverted.

15. Data transmission circuitry according to claim 13, wherein said input circuitry further comprises bit generation circuitry adapted to generate a parity bit and addition circuitry adapted to add the parity bit to n binary bits and a flag bit to form an n+2 bit binary code-word.

16. Data transmission circuitry according to claim 13, further comprising control circuitry for controlling inversion circuitry to invert data in a code-word based on a running digital sum at code-word boundaries.

17. Data transmission circuitry according to claim 13, further comprising substitution storage means for storing code-words having zero disparity and set flag bits of the code words to indicate inversion of data therein, such code-words being used to substitute for code-words which increase a running digital sum at code-word boundaries or a run length of the data signal.

18. A method of decoding data and strobe signals transmitted between first and second interconnected devices, the method comprising the steps of:

establishing a data signal path between said interconnected devices;

establishing a parallel strobe signal path between said interconnected devices;

receiving a ternary data signal comprising a sequence of trits at said second device on said data signal path, said ternary data signal carrying data comprising signal level transitions at predetermined trit boundaries;

receiving a ternary strobe signal at said second device on said strobe signal path, said ternary strobe signal carrying timing information comprising signal level transitions at trit boundaries, said ternary strobe signal having transitions at trit boundaries other than said predetermined trit boundaries;

rectifying said ternary data signal into a binary data signal and said ternary strobe signal into a binary strobe signal;

exclusive-Oring said binary data signal and said binary strobe signal to generate a receive clock signal; and

outputting said binary data signal under the control of said receive clock signal.

19. The method of claim 18, further including the step of:

checking to determine whether the code-word includes an odd number of 1'"'"'s;

wherein received code-words comprise a parity bit, the parity bit being set to ensure an odd number of ones in the code-words.

20. Data receiving circuitry for receiving encoded data and strobe signals transmitted between first and second interconnected devices;

comprising

input circuitry adapted to receive a ternary data signal and a ternary strobe signal, said ternary data signal comprising a sequence of trits and carrying data comprising signal level transitions at predetermined trit boundaries, said ternary strobe signal being parallel to said data signal path and having signal level transitions only at trit boundaries other than said predetermined trit boundaries;

rectification circuitry adapted to rectify said ternary data signal into a binary data signal and said tertiary strobe signal into a binary strobe signal;

an exclusive-OR gate arranged to receive said binary data and said binary strobe signals and to generate a receive clock signal at its output; and

output circuitry adapted to output the binary data signal under the control of the clock signal.

21. Data receiving circuitry according to claim 20, wherein received ternary code-words include a parity trit the data receiving circuitry further comprising a parity check circuit, the parity check circuit checking the parity of the received code-word based on the parity bit.

22. Data receiving circuitry according to claim 20, further comprising circuitry for calculating a disparity of each received code-word, wherein if the disparity of the code-word is zero and a flag bit of the code-word is set to indicate inversion, the data receiving circuitry further comprising storage means for storing code-words for substitution of code-words having zero disparity and flag bits which are set.

23. Data receiving circuitry according to claim 20, further comprising inversion circuitry, wherein if a disparity of the code-word is non-zero and a flag bit is set, then the inversion circuitry inverts data contained in the code-word.