Layout for measurement of overlay error

• US 6,484,060 B1
• Filed: 03/24/2000
• Issued: 11/19/2002
• Est. Priority Date: 03/24/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Baluswamy, Pary, Bossart, Tim H.
• Primary Examiner(s): Von Buhr, Maria N.
• Application Number:
  US09/533,785
• Time in Patent Office: 970 Days
• Field of Search: 700/56-59, 700/95-98, 700/108-110, 700/117-125, 356/399-401, 430/5, 430/22, 430/311-319, 438/14, 438/17, 438/18, 438/400, 438/401, 438/460, 438/462, 257/797
• US Class Current: 700/58
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In the manufacture of a multi-lay integrated circuit, a reference target is etched into a test wafer along with circuit features of a reference layer. As successive dependent layers are printed, successive dependent targets overlaying the same reference target are formed in photoresist. As each successive dependent target is printed, the degree to which it is registered with the reference target is used to determine the overlay error. After determination of overlay error for a layer, the layer'"'"'s dependent target is removed, allowing the reference target to be matched with the dependent target of another layer.

Claims

1. A method of laying out targets for a semiconductor product, said method comprising the steps of:

providing a reference target in a reference layer on a test wafer, said reference target registering subsequent layers dependent on said reference layer;

forming a dependent target in a dependant target location area of a subsequent layer dependent on said reference layer; and

removing said dependent target of said subsequent layer.

2. The method of claim 1, further comprising the step of forming at least one additional dependent target in at least one additional dependent target location area of at least one additional subsequent layer dependent on said reference layer.

3. The method of claim 2, further comprising the step of removing said at least one additional dependent target of said at least one additional subsequent layer.

4. The method of claim 1, further comprising the steps of:

forming additional dependent targets in additional dependent target location areas of a plurality of additional subsequent layers dependent on said reference layer;

removing said additional dependent targets of said additional subsequent layers.

5. The method of claim 4, further comprising the step of forming a last dependent target in a last dependent target area of a last subsequent layer dependent on said reference layer.

6. The method of claim 1, wherein said reference target is etched into said reference layer.

7. The method of claim 1, wherein said dependent target is formed of photoresist.

8. The method of claim 1, wherein said reference target comprises a square.

9. The method of claim 8, wherein said dependent target comprises a square smaller than said reference target.

10. The method of claim 1, wherein said dependent target location area is within an area bounded by said reference target.

11. A method of measuring overlay error for a multi-layer integrated circuit, said method comprising the steps of:

providing a reference target in a reference layer on a test wafer;

providing a dependent target in a dependent target location area of a subsequent layer dependent on said reference layer;

comparing said dependent target to said reference target to determine any registration errors between said subsequent layer and said reference layer; and

removing said dependent target.

12. The method of claim 11, further comprising the step of forming at least one additional reference target in at least one additional reference target location area of at least one additional subsequent layer dependent on said reference layer and comparing said at least one additional dependent target to said reference target to determine any registration errors between said at least one additional subsequent layer and said reference layer.

13. The method of claim 12, further comprising the step of removing said at least one additional dependent target of said at least one additional subsequent layer.

14. The method of claim 11, further comprising the steps of:

forming additional dependent targets in a plurality of additional subsequent layers dependent on said reference layer;

comparing said additional dependent targets to said reference target to determine any registration errors between said plurality of additional subsequent layers and said reference layer; and

removing additional dependent targets of said additional subsequent layers.

15. The method of claim 14, further comprising the step of forming a last dependent target in a last dependent target area of a last subsequent layer dependent on said reference layer and comparing said last dependent target to said reference target to determine any registration errors between said last subsequent layer and said reference layer.

16. A method of making a multi-layer integrated circuit, said method comprising the steps of:

providing a reference target in a reference layer on a test wafer, said reference target registering every subsequent layer dependent on said reference layer;

forming subsequent layers dependent on said reference layer, each of said subsequent layers having a dependent target for comparison with said reference target; and

removing said dependent targets from a prior one of said subsequent layers before having a succeeding one of said subsequent layers.

17. The method of claim 16, wherein said reference target is etched into the integrated circuit.

18. A method of making a multi-layer integrated circuit, said method comprising the steps of locating

a first dependent target in a dependent target region of a test wafer;

comparing said first dependent target to a reference target of a reference layer provided on said test wafer;

removing said first dependent target; and

subsequently, locating a second dependent target on a subsequent layer provided on said test wafer; and

comparing said second dependent target to said reference target.

19. The method of claim 18, wherein said comparison further comprises the step of determining registration errors between said subsequent layer and said reference layer.

20. The method of claim 18, further comprising the step of etching said reference target into a reference layer.

21. The method of claim 18, wherein said dependent target region is smaller than said reference target.

22. The method of claim 21, wherein said dependent target is provided in an area bounded by said reference target.