Method for adaptive test generation via feedback from dynamic emulation

• US 6,484,135 B1
• Filed: 08/30/1999
• Issued: 11/19/2002
• Est. Priority Date: 08/30/1999
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Chin, Richard, Mukherjee, Deb Aditya
• Primary Examiner(s): Jones, Hugh M.
• Assistant Examiner(s): FERRIS III, FRED O
• Application Number:
  US09/386,012
• Time in Patent Office: 1,177 Days
• Field of Search: 714/28, 714/738, 714/724, 712/1, 703/27, 703/13, 703/15, 703/23, 716/6, 716/14
• US Class Current: 703/23
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A function for adaptively generating test vectors to verify the behavior of a digital system. The function utilizes one or more user-defined verification directives for directing the generation of the test vectors to areas of interest within the digital system. An emulator of the digital system provides dynamic feedback of internal state information to the test vector generation function during the verification. The test vector generation function adaptively generates future verification test vectors based on the user-defined verification directives in view of the internal state information feedback received from the emulator.

Claims

1. An apparatus for adaptively generating test vectors used to verify the behavior of a digital system, the apparatus comprising:

a hardware model representing a relatively low-level software characterization of the digital system;

a hardware emulator representing a relatively high-level software characterization of the digital system, wherein the hardware emulator is capable of dynamically representing internal model state information;

a test generator for generating and applying a plurality of input vectors to the hardware model and the hardware emulator to produce a directed behavior; and

one or more verification directives which characterize attributes desired in the functional testing system and which direct the behavior of the test generator, wherein the test generator accesses the internal model state information represented within the hardware emulator to adaptively generate the plurality of input vectors as directed by the one or more verification directives.

2. The apparatus of claim 1, wherein the adaptively generated plurality of input vectors generate one or more transactions within the hardware model.

3. The apparatus of claim 2, wherein the one or more transactions are related.

4. The apparatus of claim 3, wherein the one or more related transactions comprise an ordered sequence of transactions.

5. The apparatus of claim 1, wherein the adaptively generated input vectors produce transactions which conflict with a pending internal state of the digital system.

6. The apparatus of claim 1, wherein the one or more verification directives include a queue management directive.

7. The apparatus of claim 1, wherein the one or more verification directives include an address conflict directive.

8. The apparatus of claim 1, wherein the one or more verification directives include a system behavior directive.

9. The apparatus of claim 1, wherein the test generator accesses the internal model state information via a software procedural interface.

10. A method for adaptively generating test vectors to verify the behavior of a digital system, the method comprising:

defining a hardware model representing a relatively low-level software characterization of the digital system;

defining a hardware emulator representing a relatively high-level software characterization of the digital system, wherein the hardware emulator is capable of dynamically representing internal model state information;

generating a plurality of input vectors to produce a directed behavior within the hardware model, wherein the generation utilizes the internal model state information represented within the hardware emulator; and

applying the plurality of input vectors to the hardware emulator and the hardware model, producing the directed behavior.

11. The method of claim 10, wherein the plurality of input vectors generate one or more transactions within the hardware model.

12. The method of claim 11, wherein the one or more transactions are related.

13. The method of claim 12, wherein the one or more related transactions comprise an ordered sequence of transactions.

14. The method of claim 10, wherein the generation utilizes one or more verification directives which characterize attributes desired in the functional testing system, and which direct the behavior of the generation.

15. The method of claim 14, wherein the plurality of input vectors produce transactions which conflict with a pending internal state of the digital system.

16. The method of claim 14, wherein the verification directives include a queue management directive.

17. The method of claim 14, wherein the verification directives include an address conflict directive.

18. The method of claim 14, wherein the verification directives include a system behavior directive.

19. A computer readable medium containing instructions for controlling a computer system to perform a method for adaptively generating test vectors for verifying the behavior of a digital system, comprising the steps of:

defining a hardware model representing a relatively low-level software characterization of the digital system;

defining a hardware emulator representing a relatively high-level software characterization of the digital system, wherein the hardware emulator is capable of dynamically representing internal model state information;

generating a plurality of input vectors to produce a directed behavior within the hardware model, wherein the generation utilizes the internal model state information represented within the hardware emulator; and

applying the plurality of input vectors to the hardware emulator and the hardware model, producing the directed behavior.