Multi-interface symmetric multiprocessor

• US 6,484,224 B1
• Filed: 11/29/1999
• Issued: 11/19/2002
• Est. Priority Date: 11/29/1999
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Robins, Kristen Marie, Kon, Ronnie B.
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US09/450,803
• Time in Patent Office: 1,086 Days
• Field of Search: 710/52, 710/305, 710/310, 709/102, 709/200, 709/213, 709/232, 370/412, 370/413, 370/419
• US Class Current: 710/305
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface. The second inbound interface receives incoming packets and has a second input buffer maintaining a second input queue of the packets. The second outbound interface receives packets from the second processor and transmits outgoing packets. The second task queue receives packets output from at least the first processor and maintains another input queue of the packets for processing by the second processor and which are outgoing from the second outbound interface. The first processor executes a process thread on packets by requesting the packets from the first input queue and the first task queue in a predetermined manner. The second processor executes a process thread on packets by requesting the packets from the second input queue and the second task queue in a predetermined manner.

Claims

1. A symmetric multiprocessor system comprising:

a first processor and a second processor for executing a multi-threaded process on packets;

a first inbound interface device associated with said first processor, said first inbound interface device receiving incoming packets and having a first input buffer accessible by said first processor, said first input buffer maintaining a queue of the packets received on said first inbound interface device;

a first outbound interface device associated with said first processor, said first outbound interface device receiving packets output from said first processor and transmitting said packets therefrom;

a first task queue accessible for reading by said first processor, said first task queue receiving packets output from at least said second processor, the packets in said first task queue being transmitted from said first outbound interface device;

a second inbound interface device associated with said second processor, said second inbound interface device receiving incoming packets and having a second input buffer accessible for reading by said second processor, said second input buffer maintaining a queue of the packets received on said second inbound interface device;

a second outbound interface device associated with said second processor, said second outbound interface receiving packets output from said second processor and transmitting said packets therefrom; and

a second task queue accessible for reading by said second processor, said second task queue receiving packets output from at least said first processor. The packets in said second task queue being transmitted from said second outbound interface device.

3. A symmetric multiprocessor system according to claim 1, wherein said first processor executes a first process thread on packets by requesting packets from said first input buffer and said first task queue in a predetermined manner.

4. A symmetric multiprocessor system according to claim 1, wherein said second processor executes a second process thread on packets by requesting packets from said second input buffer and said second task queue in a predetermined manner.

5. A symmetric multiprocessor system according to claim 1, wherein said first processor sends a packet to said second task queue when the packet is to be transmitted from said second outbound interface device.

6. A symmetric multiprocessor system according to claim 1, wherein said second processor sends a packet to said first task queue when the packet is to be transmitted from said first outbound interface device.

7. A symmetric multiprocessor system according to claim 1, further comprising a third processor executing a process.

8. A symmetric multiprocessor system according to claim 7, wherein said first task queue also receives packets output from said third processor.

9. A symmetric multiprocessor system according to claim 7, wherein said second task queue also receives packets output from said third processor.

10. A symmetric multiprocessor system according to claim 7, further comprising a third task queue accessible for reading by said third processor, wherein said first processor sends a packet to said third task queue when the packet is to be processed by said process executed by said third processor.

11. A symmetric multiprocessor system according to claim 1 wherein said first and second processors operate under instructions to perform at least one of (a) decapsulating a packet;

(b) examining the destination of a packet;

(c) determining a path of a packet;

(d) selecting an outbound interface device for a packet; and

(e) encapsulating a packet.

12. A symmetric multiprocessor system according to claim 11 wherein said first and second processors send a packet to a buffer for packets to be discarded when the packet has no valid destination.

13. A symmetric multiprocessor system according to claim 1, further comprising:

a third inbound interface device associated with said first processor, said third inbound interface device receiving incoming packets and having a third input buffer accessible for reading by said first processor, said third input buffer maintaining a queue of the packets received on said third inbound interface device; and

a third outbound interface device associated with said first processor, said third outbound interface device associated with said first processor and receiving packets output from said first processor and transmitting said packets therefrom.

14. A symmetric multiprocessor system according to claim 13, wherein said second processor sends a packet to said first task queue when the packet is to be transmitted from one of said first and third outbound interface devices.

15. A symmetric multiprocessor system according to claim 13, wherein said first processor requests packets from said first input buffer, said third input buffer, and said first task queue in a predetermined manner.

16. A symmetric multiprocessor system according to claim 1, further comprising:

a fourth inbound interface device associated with said second processor, said fourth inbound interface device receiving incoming packets and having a fourth input buffer accessible for reading by said second processor, said fourth input buffer maintaining a queue of the packets received on said fourth inbound interface device; and

a fourth outbound interface device associated with said second processor, said fourth outbound interface device receiving packets output from said second processor and transmitting said packets therefrom.

17. A symmetric multiprocessor system according to claim 16, wherein said first processor sends a packet to said second task queue when the packet is to be transmitted from one of said second and fourth outbound interface devices.

18. A symmetric multiprocessor system according to claim 16, wherein said first processor requests packets from said second input queue, said fourth input queue, and said second task queue in a predetermined manner.

2. A symmetric multiprocessor system comprising:

a first processor and a second processor for executing a multi-threaded process on packets;

a first inbound interface device associated with said first processor, said first inbound interface device receiving incoming packets and having a first input buffer accessible by said first processor, said first input buffer maintaining a queue of the packets received on said first inbound interface device;

a first outbound interface device associated with said first processor, said first outbound interface device receiving packets output from said first processor and transmitting said packets therefrom;

a first task queue accessible for reading by said first processor, said first task queue receiving packets output from at least said second processor, the packets in said first task queue being transmitted from said first outbound interface device;

a second outbound interface device associated with said second processor, said second outbound interface receiving packets output from said second processor and transmitting said packets therefrom; and

a second task queue accessible for reading by said second processor, said second task queue receiving packets output from at least said first processor. The packets in said second task queue being transmitted from said second outbound interface device.

19. A method for operating a symmetric multiprocessor system including a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface device, a first outbound interface device, a first task queue associated with said first processor, a second inbound interface device, a second outbound interface device, and a second task queue associated with said second processor, said method comprising:

receiving incoming packets on said first inbound interface device;

maintaining a queue of packets received on said first inbound interface device in a first input buffer;

receiving packets in said first task queue, said packets received from at least said second processor, said packets for transmission from said first outbound interface device;

maintaining a queue of packets received in said first task queue;

requesting a packet from one of said first input buffer and said first task queue in a predetermined manner;

executing a first process thread on said requested packet;

sending said packet processed by said first process thread to said second task queue when said packet is to be transmitted from said second outbound interface device; and

outputting said packet processed by said first process thread to said first outbound interface device when said packet is to be transmitted from said first outbound interface device.

20. A method according to claim 19, further comprising:

receiving incoming packets on said second inbound interface device;

maintaining a queue of packets received on said second inbound interface device in a second input buffer;

receiving packets in said second task queue, said packets received from at least said first processor, said packets for transmission from said second outbound interface device;

maintaining a queue of packets received in said second task queue;

requesting a packet from one of said second input buffer and second task queue in a predetermined manner;

executing a second process thread on said requested packet;

sending said packet processed by said second process thread to said first task queue when the packet is to be transmitted from said first outbound interface device; and

outputting said packet processed by said second thread to said second outbound interface device when said packet is to be transmitted from said second outbound interface device.

21. A method according to claim 19, further comprising executing a third process by a third processor, wherein said receiving packets in said first task queue includes receiving packets output from said third processor.

22. A method according to claim 21, wherein said system further includes a third task queue accessible for reading by said third processor, and said method further comprises:

sending a packet processed by said first process thread to said third task queue when the packet is to be processed by said third process.

23. A method according to claim 20, wherein said receiving packets in said second task queue includes receiving packets output from said third processor, and said method further comprises:

executing a third process on a third processor.

24. A method according to claim 23, wherein said system further includes a third task queue accessible for reading by said third processor, and said method further comprises:

sending a packet processed by said second process thread to said third task queue when the packet is to be processed by said third process.

25. A method according to claim 19, wherein said executing a first process thread includes at least one of:

decapsulating a packet;

examining a destination of a packet;

determining a path of a packet'"'"' selecting an outbound interface device for a packet and encapsulating a packet.

26. A method according to claim 20, wherein said executing a second process thread includes at least one of:

decapsulating a packet;

examining a destination of a packet;

determining a path of a packet,;

selecting an outbound interface device for a packet; and

encapsulating a packet.

27. A method according to claim 20, wherein said system includes a third inbound interface device and a third outbound interface device, and said method further comprises:

receiving incoming packets on said third inbound interface device;

maintaining a queue of the packets received on said third inbound interface device in a third input buffer;

requesting a packet from said third input buffer in a predetermined manner;

executing said first process thread on said packet;

sending said packet processed by said first process thread to said second task queue when said packet is to be transmitted from said second outbound interface device;

outputting said packet processed by said first process thread to said third outbound interface device when said packet is to be sent from said third outbound interface device; and

sending a packet processed by said second process thread to said first task queue when said packet is to be transmitted from said third outbound interface device.

28. A method according to claim 27, wherein said system includes a fourth inbound interface device and a fourth outbound interface device, and said method further comprises:

receiving incoming packets on said fourth inbound interface device;

maintaining a queue of the packets received on said fourth inbound interface device in a fourth input buffer;

requesting a packet from said fourth input buffer in a predetermined manner;

executing said second process thread on said packet;

sending said packet processed by said second process thread to said first task queue when said packet is to be transmitted from one of said first outbound interface and said third outbound interface devices; and

outputting said packet processed by said second process thread to said fourth outbound interface device when said packet is to be sent from said fourth outbound interface device.

29. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for operating a symmetric multiprocessor system including a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface device, a first outbound interface device, a first task queue associated with said first processor, a second inbound interface device, a second outbound interface device, and a second task queue associated with said second processor, said method comprising:

receiving incoming packets on said first inbound interface device;

maintaining a queue of packets received on said first inbound interface device in a first input buffer;

receiving packets in said first task queue, said packets received from at least said second processor, said packets for transmission from said first outbound interface device;

maintaining a queue of packets received in said first task queue;

requesting a packet from one of said first input buffer and said first task queue in a predetermined manner;

executing a first process thread on said requested packet;

sending said packet processed by said first process thread to said second task queue when said packet is to be transmitted from said second outbound interface device; and

outputting said packet processed by said first process thread to said first outbound interface device when said packet is to be transmitted from said first outbound interface device.

30. A symmetric multiprocessor system comprising:

a first processor;

a first inbound interface associated with said first processor, said first inbound interface receiving task for processing by said first processor;

a second processor;

a second inbound interface associated with said second processor, said second inbound interface receiving tasks for processing by said second processor;

a task queue readable by said second processor and writeable by said first processor, said task queue receiving task for processing by said second processor;

an outbound interface associated with said second processor, said outbound interface capable of receiving an output associated with tasks performed by said second processor; and

a task switcher selecting a task for performing by said second processor from among said second inbound interface and said task queue.

31. A symmetric multiprocessor system comprising:

a first processor;

a first inbound interface associated with said first processor, said first inbound interface receiving tasks for processing by said first processor;

a first outbound interface associated with said first processor, said first outbound interface capable of receiving an output associated with tasks performed by said first processor;

a second processor;

a second inbound interface associated with said second processor, said second inbound interface receiving tasks for processing by said second processor;

a second outbound interface associated with said second processor, said second outbound interface capable of receiving an output associated with tasks performed by said second processor;

a first task queue readable by said second processor and writeable by said first processor, said first task queue receiving tasks for processing by said second processor;

a second task queue readable by said first processor and writeable by said second processor, said second task queue receiving tasks for processing by said first processor;

a first task switcher selecting a task for performing by said first processor from among said first inbound interface and said first task queue; and

a second task switcher selecting a task for performing by said second processor from among said second inbound interface and said second task queue.