Clock gated bus keeper

• US 6,484,267 B1
• Filed: 12/29/1999
• Issued: 11/19/2002
• Est. Priority Date: 12/29/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Lee, Hyun, Potter, David W.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/474,413
• Time in Patent Office: 1,056 Days
• Field of Search: 713/600, 710/100, 710/104, 710/126
• US Class Current: 713/600
• CPC Class Codes: G06F 13/4077 Precharging or discharging

Abstract

The present invention comprises a clocked bus keeper circuit that does not drive the bus during the first half of a clock cycle and then holds the value driven onto the bus during the first half of the clock cycle for the second half of the clock cycle. Accordingly, true data drivers on the bus drive the bus during the first half of the clock cycle without the need to overcome the value driven by the bus keeper, but during the second half of the clock cycle, the bus keeper holds the data driven during the first half of the clock cycle. In this manner, there is no bus contention between the true bus data drivers and the bus keeper.

Claims

1. A method of driving a bus with data, said method comprising the steps of:

(1) clocking said bus with a clock having a clock cycle comprising a first transition edge followed by a phase having a first logic level and a second transition edge followed by a phase having a second logic level;

(2) turning a driver on to drive said bus with data responsive to said first edge of said clock cycle;

(3) turning said driver off responsive to said second edge of said clock cycle;

(4) turning a bus keeper off responsive to said first edge of said clock cycle; and

(5) turning said bus keeper on responsive to said second edge of said clock cycle.

2. The method as set forth in claim 1 wherein said bus keeper is directly responsive to said clock.

3. The method as set forth in claim 1 wherein said bus comprises at least one bit line, said driver can alternately drive said bit line to a third logic level and a fourth logic level and wherein step (4) comprises:

(4.1) coupling a node of said bus keeper to said bit line of said bus;

(4.2) allowing said node to align with the logic level driven onto said bus bit line by the driver during the first phase of the clock cycle;

(4.3) coupling said node to a first voltage source having said third logic level during said second phase of said clock cycle, if said bus was driven to said first logic level during the first phase of the corresponding clock cycle; and

(4.4) coupling said node to second voltage source having said fourth logic level during said second phase of said clock cycle, if said bus was driven to said second logic level during the first phase of the corresponding clock cycle.

4. The method as set forth in claim 3 wherein step (4.3) comprises;

(4.3.1) coupling said node to said first voltage source through a first transistor circuit;

(4.3.2) turning said first transistor circuit off during said first phase of said clock cycle so that said node is not coupled to said first voltage source; and

(4.3.3) turning said first transistor circuit on during said second phase of said clock cycle so that said node is coupled to said first voltage source, if a logic level on said bus at said second edge of said clock cycle is said third logic level;

and wherein step (4.4) comprises

(4.4.1) coupling said node to said second voltage source through a second transistor circuit;

(4.4.2) turning said second transistor circuit off during said first phase of said clock cycle so that said node is not coupled to said second voltage source; and

(4.4.3) turning said second transistor circuit on during said second phase of said clock cycle so that said node is coupled to said second voltage source, if a logic level on said bus at said second edge of said clock cycle is said second logic level.

5. The method as set forth in claim 4 wherein said first and third logic levels are the same and said second and fourth logic levels are the same.

6. A method of driving a bus with data, said method comprising the steps of:

(1) clocking said bus with a clock having a clock cycle comprising a first phase having a first logic level and a second phase having a second logic level;

(2) turning a driver on to drive said bus with data during said first phase of said clock cycle;

(3) turning said driver off during said second phase of said clock cycle;

(4) turning a bus keeper on during said second phase of said clock cycle; and

(5) turning said bus keeper off during said first phase of said clock cycle.

7. The method as set forth in claim 6 wherein said bus keeper is directly responsive to said clock.

8. The method as set forth in claim 6 wherein said bus comprises at least one bit line, said driver can alternately drive said bit line to a third logic level and a fourth logic level and wherein step (4) comprises:

(4.1) coupling a node of said bus keeper to said bit line of said bus;

(4.2) allowing said node to align with the logic level driven onto the bus bit line by the driver during the first phase of the clock cycle;

(4.3) during said second phase of said clock cycle, coupling said node to one of a first voltage source having said third voltage level and a second voltage source having said fourth logic level, responsive to said bus having been driven to said third logic level or said fourth logic level during the first phase of the corresponding clock cycle, respectively.

9. The method as set forth in claim 8 wherein step (4.3) comprises;

(4.3.1) coupling said node to said first voltage source or said second voltage source through a first transistor circuit and a second transistor circuit, respectively;

(4.3.2) turning said first and second transistor circuits off during said first phase of said clock cycle so that said node is not coupled to said first voltage source or said second voltage source; and

(4.3.3) turning said first transistor circuit on during said second phase of said clock cycle so that said node is coupled to said first voltage source, if a logic level on said bus at said second edge of said clock cycle is said third logic level and turning said second transistor circuit on during said second phase of said clock cycle so that said node is coupled to said second voltage source, if a logic level on said bus at said second edge of said clock cycle is said fourth logic level.

10. A bus keeper circuit for a bus circuit, said bus circuit comprising at least a first bus bit line that can be driven to a first or a second logic level and a bus clock having a clock cycle comprising a first transition edge followed by a first phase and a second transition edge followed by a second phase, said bus keeper circuit comprising:

a node coupled to said bus bit line;

a first circuit coupled between said node and a first voltage source producing a voltage equal to said first logic level;

a second circuit coupled between said node and a second voltage source producing a voltage equal to said second logic level;

said first and second circuits being responsive to said clock phase such that said first and second circuits decouple said node from said first and second voltage sources, respectively, during said first phase of said clock cycle such that said node aligns with said voltage on said bus bit line;

said first and second circuits further being responsive to said bus bit line such that one of said first and second circuits is turned on so as to electrically couple said node to one of said first and second voltage sources, respectively, responsive to said logic level on said bus bit line at said second transition of said clock cycle.

11. The bus keeper circuit as set forth in claim 10 wherein said node is coupled directly to said bus bit line.

12. The bus keeper circuit as set forth in claim 11 wherein each of said first and second circuits comprise first and second transistors having their current flow terminals coupled in series between said corresponding voltage source and said node and wherein each of said first transistors has a control terminal coupled to said clock such that said transistor is turned off responsive to said clock being in said first phase.

13. The bus keeper circuit as set forth in claim 12 wherein said control terminal of at least one of said first transistors is coupled directly to said clock.

14. The bus keeper circuit as set forth in claim 12 wherein each of said second transistors has a control terminal coupled to said bus bit line such that said first logic level on said bus bit line turns said second transistor of said first circuit on and said second transistor of said second circuit off and said second logic level on said bus bit line turns said second transistor of said first circuit off and said second transistor of said second circuit on;

whereby, during said second phase of said clock cycle, said node is coupled to the one of said first and second voltage sources that corresponds to said logic level on said bus bit line at said second transition of said clock cycle.

15. The bus keeper circuit as set forth in claim 14 further comprising a first inverter coupled between said bus bit line and said control terminals of said second transistors of said first and second circuits.

16. The bus keeper circuit as set forth in claim 15 further comprising a second inverter coupled between said clock and said control terminal of one and only one of said first transistor of said first circuit and said first transistor of said second circuit.

17. The bus keeper circuit as set forth in claim 10 wherein said bus keeper circuit is embodied on a system-on-a-chip integrated circuit.

18. A bus keeper circuit for a bus circuit, said bus circuit comprising at least a first bus bit line that can be driven to a first or a second logic level and a bus clock having a clock cycle comprising a first transition edge followed by a first phase having a third logic level and a second transition edge followed by a second phase having a fourth logic level, said bus keeper circuit comprising:

a node coupled to said bit line of said bus;

a first transistor having a control terminal coupled to said bus bit line, a first current flow terminal coupled to said node, and a second current flow terminal;

a second transistor having a control terminal coupled to said clock, a first current flow terminal coupled to a first voltage source producing a voltage having said first voltage level, and a second current flow terminal coupled to said second current flow terminal of said first transistor;

a third transistor having a control terminal coupled to said bus bit line, a first current flow terminal coupled to said node, and a second current flow terminal;

a fourth transistor having a control terminal coupled to said clock, a first current flow terminal a second voltage source producing a voltage having said second voltage level and, a second current flow terminal coupled to said second current flow terminal of said third transistor;

wherein said control terminals of said second and fourth transistors are coupled to said clock such that said transistors are turned off responsive to said clock being in said first phase and turned on responsive to said clock being in said second phase; and

wherein said control terminals of said first and third transistors are coupled to said bus bit line such that said first logic level on said bus turns on said first transistor and turns off said third transistor and said second logic level on said bus turns off said first transistor and turns on said third transistor.

19. The bus keeper circuit as set forth in claim 18 wherein said control terminal of said second transistor is coupled directly to said clock and said control terminal of said fourth transistor is coupled to said clock through a first inverter.

20. The bus keeper circuit as set forth in claim 19 wherein said control terminals of said first and third transistors are coupled to said bus through a second inverter.

21. The bus keeper circuit as set forth in claim 20 wherein said first and third transistors are complementary.

22. The bus keeper circuit as set forth in claim 21 wherein said second and fourth transistors are complementary.

23. The bus keeper circuit as set forth in claim 22 wherein said first and second transistors are of the same type.

24. The bus keeper circuit as set forth in claim 23 wherein said first and second transistors are n-type transistors and said third and fourth transistors are p-type transistors.

25. The bus keeper circuit as set forth in claim 24 wherein said bus keeper circuit is embodied on a system-on-a-chip integrated circuit.

26. The bus keeper circuit as set forth in claim 18 wherein said bus keeper circuit is embodied on a system-on-a-chip integrated circuit.